Re: [PATCH] Revert "drm/amd/display: Tune min clk values for MPO for RV"

[Harry Wentland <harry.wentland@xxxxxxx>]

On 2021-01-18 6:03 a.m., Pratik Vishwakarma wrote:
> This reverts commit 6f3fca64cfb91fedf9b34ea27b2581e88d48c9b2.
> Flash line issue when MPO enabled on idle screen was fixed by
> commit 9d03bb102028 ("drm/amd/display: disable dcn10 pipe split by default")
>
> This patch is no more required

Do you have additional details? I'm curious how/where this was fixed, or 
why this is not required anymore.

Harry

> Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@xxxxxxx>
> ---
>   .../display/dc/clk_mgr/dcn10/rv1_clk_mgr.c    | 30 ++-----------------
>   1 file changed, 3 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
> index 75b8240ed059..e133edc587d3 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
> @@ -187,17 +187,6 @@ static void ramp_up_dispclk_with_dpp(
>   	clk_mgr->base.clks.max_supported_dppclk_khz = new_clocks->max_supported_dppclk_khz;
>   }
>   
> -static bool is_mpo_enabled(struct dc_state *context)
> -{
> -	int i;
> -
> -	for (i = 0; i < context->stream_count; i++) {
> -		if (context->stream_status[i].plane_count > 1)
> -			return true;
> -	}
> -	return false;
> -}
> -
>   static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
>   			struct dc_state *context,
>   			bool safe_to_lower)
> @@ -295,22 +284,9 @@ static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
>   		if (pp_smu->set_hard_min_fclk_by_freq &&
>   				pp_smu->set_hard_min_dcfclk_by_freq &&
>   				pp_smu->set_min_deep_sleep_dcfclk) {
> -			// Only increase clocks when display is active and MPO is enabled
> -			if (display_count && is_mpo_enabled(context)) {
> -				pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu,
> -						((new_clocks->fclk_khz / 1000) *  101) / 100);
> -				pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu,
> -						((new_clocks->dcfclk_khz / 1000) * 101) / 100);
> -				pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu,
> -						(new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
> -			} else {
> -				pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu,
> -						new_clocks->fclk_khz / 1000);
> -				pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu,
> -						new_clocks->dcfclk_khz / 1000);
> -				pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu,
> -						(new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
> -			}
> +			pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, new_clocks->fclk_khz / 1000);
> +			pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, new_clocks->dcfclk_khz / 1000);
> +			pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
>   		}
>   	}
>   }
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