On Wed, Jan 13, 2021 at 07:22:04PM +0800, Du, Xiaojian wrote:
> This patch is to modify the fine grain tuning function for vangogh.
> It is risky to add two new flags to common smu struct.
> So this patch uses the existing old flag to make the two sysfs files
> work separately -- "power_dpm_force_performance_level" and
> "pp_od_clk_voltage".
> Only the power_dpm_force_performance_level is switched to "manual"
> mode, the fine grain tuning function will be started.
> In other mode, including "high","low","min_sclk","min_mclk",
> "standard" and "peak", the fine grain tuning function will be shut down,
> and the frequency range of gfx and cpu clock will be restored the
> default values.
>
> Signed-off-by: Xiaojian Du <Xiaojian.Du@xxxxxxx>
Series are Reviewed-by: Huang Rui <ray.huang@xxxxxxx>
> ---
> drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 3 --
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 -
> .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 52 +++++++++++++++++--
> 3 files changed, 48 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> index 277559e80961..25ee9f51813b 100644
> --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> @@ -466,9 +466,6 @@ struct smu_context
> uint32_t gfx_actual_hard_min_freq;
> uint32_t gfx_actual_soft_max_freq;
>
> - bool fine_grain_enabled;
> - bool fine_grain_started;
> -
> uint32_t cpu_default_soft_min_freq;
> uint32_t cpu_default_soft_max_freq;
> uint32_t cpu_actual_soft_min_freq;
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index 976a9105aecc..7fe61ad3ed10 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -419,8 +419,6 @@ static int smu_set_funcs(struct amdgpu_device *adev)
> break;
> case CHIP_VANGOGH:
> vangogh_set_ppt_funcs(smu);
> - /* enable the OD by default to allow the fine grain tuning function */
> - smu->od_enabled = true;
> break;
> default:
> return -EINVAL;
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> index b49044825680..3e32b223d47b 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> @@ -438,6 +438,7 @@ static int vangogh_print_fine_grain_clk(struct smu_context *smu,
> {
> DpmClocks_t *clk_table = smu->smu_table.clocks_table;
> SmuMetrics_t metrics;
> + struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
> int i, size = 0, ret = 0;
> uint32_t cur_value = 0, value = 0, count = 0;
> bool cur_value_match_level = false;
> @@ -450,7 +451,7 @@ static int vangogh_print_fine_grain_clk(struct smu_context *smu,
>
> switch (clk_type) {
> case SMU_OD_SCLK:
> - if (smu->od_enabled) {
> + if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
> size = sprintf(buf, "%s:\n", "OD_SCLK");
> size += sprintf(buf + size, "0: %10uMhz\n",
> (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
> @@ -459,7 +460,7 @@ static int vangogh_print_fine_grain_clk(struct smu_context *smu,
> }
> break;
> case SMU_OD_CCLK:
> - if (smu->od_enabled) {
> + if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
> size = sprintf(buf, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select);
> size += sprintf(buf + size, "0: %10uMhz\n",
> (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);
> @@ -468,7 +469,7 @@ static int vangogh_print_fine_grain_clk(struct smu_context *smu,
> }
> break;
> case SMU_OD_RANGE:
> - if (smu->od_enabled) {
> + if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
> size = sprintf(buf, "%s:\n", "OD_RANGE");
> size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
> smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
> @@ -1127,15 +1128,39 @@ static int vangogh_set_performance_level(struct smu_context *smu,
>
> switch (level) {
> case AMD_DPM_FORCED_LEVEL_HIGH:
> + smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
> + smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
> +
> + smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
> + smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
> +
> ret = vangogh_force_dpm_limit_value(smu, true);
> break;
> case AMD_DPM_FORCED_LEVEL_LOW:
> + smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
> + smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
> +
> + smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
> + smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
> +
> ret = vangogh_force_dpm_limit_value(smu, false);
> break;
> case AMD_DPM_FORCED_LEVEL_AUTO:
> + smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
> + smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
> +
> + smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
> + smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
> +
> ret = vangogh_unforce_dpm_levels(smu);
> break;
> case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
> + smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
> + smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
> +
> + smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
> + smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
> +
> ret = smu_cmn_send_smc_msg_with_param(smu,
> SMU_MSG_SetHardMinGfxClk,
> VANGOGH_UMD_PSTATE_STANDARD_GFXCLK, NULL);
> @@ -1165,6 +1190,12 @@ static int vangogh_set_performance_level(struct smu_context *smu,
>
> break;
> case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
> + smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
> + smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
> +
> + smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
> + smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
> +
> ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinVcn,
> VANGOGH_UMD_PSTATE_PEAK_DCLK, NULL);
> if (ret)
> @@ -1176,6 +1207,12 @@ static int vangogh_set_performance_level(struct smu_context *smu,
> return ret;
> break;
> case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
> + smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
> + smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
> +
> + smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
> + smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
> +
> ret = vangogh_get_profiling_clk_mask(smu, level,
> NULL,
> NULL,
> @@ -1189,6 +1226,12 @@ static int vangogh_set_performance_level(struct smu_context *smu,
> vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask);
> break;
> case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
> + smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
> + smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
> +
> + smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
> + smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
> +
> ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
> VANGOGH_UMD_PSTATE_PEAK_GFXCLK, NULL);
> if (ret)
> @@ -1401,8 +1444,9 @@ static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TAB
> {
> int ret = 0;
> int i;
> + struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
>
> - if (!smu->od_enabled) {
> + if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) {
> dev_warn(smu->adev->dev, "Fine grain is not enabled!\n");
> return -EINVAL;
> }
> --
> 2.17.1
>
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