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[AMD Official Use Only - Internal Distribution Only]
Acked-by: Alex Deucher <alexander.deucher@xxxxxxx>
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> on behalf of Hawking Zhang <Hawking.Zhang@xxxxxxx>
Sent: Tuesday, December 22, 2020 6:10 AM To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx <amd-gfx@xxxxxxxxxxxxxxxxxxxxx>; Sierra Guiza, Alejandro (Alex) <Alex.Sierra@xxxxxxx>; Jian, Jane <Jane.Jian@xxxxxxx> Cc: Zhang, Hawking <Hawking.Zhang@xxxxxxx> Subject: [PATCH] drm/amdgpu: drop psp ih programming for sriov guest on navi the psp access ih path is not needed in navi
Signed-off-by: Hawking Zhang <Hawking.Zhang@xxxxxxx> Change-Id: Ib68bfb1b13e1cec03ec27bc9a867e2b37fc2fc8a --- drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 18 ++---------------- 1 file changed, 2 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c index 060357625504..f4e4040bbd25 100644 --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c @@ -151,14 +151,7 @@ static int navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev, /* enable_intr field is only valid in ring0 */ if (ih == &adev->irq.ih) tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); - if (amdgpu_sriov_vf(adev)) { - if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { - dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); - return -ETIMEDOUT; - } - } else { - WREG32(ih_regs->ih_rb_cntl, tmp); - } + WREG32(ih_regs->ih_rb_cntl, tmp); if (enable) { ih->enabled = true; @@ -268,14 +261,7 @@ static int navi10_ih_enable_ring(struct amdgpu_device *adev, tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0); tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); } - if (amdgpu_sriov_vf(adev)) { - if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { - dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); - return -ETIMEDOUT; - } - } else { - WREG32(ih_regs->ih_rb_cntl, tmp); - } + WREG32(ih_regs->ih_rb_cntl, tmp); if (ih == &adev->irq.ih) { /* set the ih ring 0 writeback address whether it's enabled or not */ -- 2.17.1 _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://nam11.safelinks.protection.outlook.com/?url=""> |
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