Series is:
Reviewed-by: Alex Deucher <alexander.deucher@xxxxxxx>
On Wed, Dec 9, 2020 at 10:29 AM Hawking Zhang <Hawking.Zhang@xxxxxxx> wrote:
>
> GUI_IDLE interrupts controlled by CP_INT_CNTL_RING0
> are only applicable to me0 pipe0.
>
> For ASICs that have gfx pipe removed, don't toggle
> those bits.
>
> Signed-off-by: Hawking Zhang <Hawking.Zhang@xxxxxxx>
> Reviewed-by: Feifei Xu <Feifei.Xu@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index ef430f285472..5f4805e4d04a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -2633,7 +2633,14 @@ static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
> static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
> bool enable)
> {
> - u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
> + u32 tmp;
> +
> + /* don't toggle interrupts that are only applicable
> + * to me0 pipe0 on AISCs that have me0 removed */
> + if (!adev->gfx.num_gfx_rings)
> + return;
> +
> + tmp= RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
>
> tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
> tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
> --
> 2.17.1
>
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