Reviewed-by: Huang Rui <ray.huang@xxxxxxx>
On Wed, Dec 09, 2020 at 10:19:24AM +0800, Deucher, Alexander wrote:
> [AMD Official Use Only - Internal Distribution Only]
>
> Acked-by: Alex Deucher <alexander.deucher@xxxxxxx>
> __________________________________________________________________
>
> From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> on behalf of
> Changfeng.Zhu <changfeng.zhu@xxxxxxx>
> Sent: Tuesday, December 8, 2020 9:06 PM
> To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx <amd-gfx@xxxxxxxxxxxxxxxxxxxxx>;
> Huang, Ray <Ray.Huang@xxxxxxx>
> Cc: Zhu, Changfeng <Changfeng.Zhu@xxxxxxx>
> Subject: [PATCH] drm/amd/pm: update smu10.h WORKLOAD_PPLIB setting for
> raven
>
> From: changzhu <Changfeng.Zhu@xxxxxxx>
> From: Changfeng <Changfeng.Zhu@xxxxxxx>
> When using old WORKLOAD_PPLIB setting in smu10.h, there is problem that
> it can't be able to switch to mak gpu clk during compute workload.
> It needs to update WORKLOAD_PPLIB setting to fix this issue.
> Change-Id: Id2160a7b4a6cb8808d100de25e999714a7ccaebd
> Signed-off-by: Changfeng <Changfeng.Zhu@xxxxxxx>
> ---
> drivers/gpu/drm/amd/pm/inc/smu10.h | 14 ++++++--------
> .../gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 9 +++------
> 2 files changed, 9 insertions(+), 14 deletions(-)
> diff --git a/drivers/gpu/drm/amd/pm/inc/smu10.h
> b/drivers/gpu/drm/amd/pm/inc/smu10.h
> index b96520528240..9e837a5014c5 100644
> --- a/drivers/gpu/drm/amd/pm/inc/smu10.h
> +++ b/drivers/gpu/drm/amd/pm/inc/smu10.h
> @@ -136,14 +136,12 @@
> #define FEATURE_CORE_CSTATES_MASK (1 << FEATURE_CORE_CSTATES_BIT)
>
> /* Workload bits */
> -#define WORKLOAD_DEFAULT_BIT 0
> -#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1
> -#define WORKLOAD_PPLIB_POWER_SAVING_BIT 2
> -#define WORKLOAD_PPLIB_VIDEO_BIT 3
> -#define WORKLOAD_PPLIB_VR_BIT 4
> -#define WORKLOAD_PPLIB_COMPUTE_BIT 5
> -#define WORKLOAD_PPLIB_CUSTOM_BIT 6
> -#define WORKLOAD_PPLIB_COUNT 7
> +#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0
> +#define WORKLOAD_PPLIB_VIDEO_BIT 2
> +#define WORKLOAD_PPLIB_VR_BIT 3
> +#define WORKLOAD_PPLIB_COMPUTE_BIT 4
> +#define WORKLOAD_PPLIB_CUSTOM_BIT 5
> +#define WORKLOAD_PPLIB_COUNT 6
>
> typedef struct {
> /* MP1_EXT_SCRATCH0 */
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> index 04226b1544e4..e57e64bbacdc 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> @@ -1298,15 +1298,9 @@ static int
> conv_power_profile_to_pplib_workload(int power_profile)
> int pplib_workload = 0;
>
> switch (power_profile) {
> - case PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT:
> - pplib_workload = WORKLOAD_DEFAULT_BIT;
> - break;
> case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
> pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
> break;
> - case PP_SMC_POWER_PROFILE_POWERSAVING:
> - pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT;
> - break;
> case PP_SMC_POWER_PROFILE_VIDEO:
> pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
> break;
> @@ -1316,6 +1310,9 @@ static int
> conv_power_profile_to_pplib_workload(int power_profile)
> case PP_SMC_POWER_PROFILE_COMPUTE:
> pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
> break;
> + case PP_SMC_POWER_PROFILE_CUSTOM:
> + pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT;
> + break;
> }
>
> return pplib_workload;
> --
> 2.17.1
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> References
>
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