RE: [PATCH 2/2] drm/amd/pm: correct power limit setting for SMU V11

["Lazar, Lijo" <Lijo.Lazar@xxxxxxx>]

[AMD Public Use]

>* BIT 24-31: ControllerId (hardcoded as PPT0)

May be reworded as 'only PPT0 is supported'. Apart from that

Series is Reviewed-by: Lijo Lazar <lijo.lazar@xxxxxxx> 

-----Original Message-----
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Evan Quan
Sent: Monday, December 7, 2020 2:53 PM
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Quan, Evan <Evan.Quan@xxxxxxx>
Subject: [PATCH 2/2] drm/amd/pm: correct power limit setting for SMU V11

[CAUTION: External Email]

Correct the power limit setting for SMU V11 asics.

Change-Id: Idedc590c35934397bd77b7ac825b063cd319dbbf
Signed-off-by: Evan Quan <evan.quan@xxxxxxx>
---
 .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c    | 23 ++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index 624065d3c079..3288760a5431 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -929,9 +929,13 @@ int smu_v11_0_get_current_power_limit(struct smu_context *smu,
        if (power_src < 0)
                return -EINVAL;

+       /*
+        * BIT 24-31: ControllerId (hardcoded as PPT0)
+        * BIT 16-23: PowerSource
+        */
        ret = smu_cmn_send_smc_msg_with_param(smu,
                                          SMU_MSG_GetPptLimit,
-                                         power_src << 16,
+                                         (0 << 24) | (power_src << 16),
                                          power_limit);
        if (ret)
                dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__); @@ -941,6 +945,7 @@ int smu_v11_0_get_current_power_limit(struct smu_context *smu,

 int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)  {
+       int power_src;
        int ret = 0;

        if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { @@ -948,6 +953,22 @@ int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
                return -EOPNOTSUPP;
        }

+       power_src = smu_cmn_to_asic_specific_index(smu,
+                                       CMN2ASIC_MAPPING_PWR,
+                                       smu->adev->pm.ac_power ?
+                                       SMU_POWER_SOURCE_AC :
+                                       SMU_POWER_SOURCE_DC);
+       if (power_src < 0)
+               return -EINVAL;
+
+       /*
+        * BIT 24-31: ControllerId (hardcoded as PPT0)
+        * BIT 16-23: PowerSource
+        * BIT 0-15: PowerLimit
+        */
+       n &= 0xFFFF;
+       n |= 0 << 24;
+       n |= (power_src) << 16;
        ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n, NULL);
        if (ret) {
                dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
--
2.29.0

_______________________________________________
amd-gfx mailing list
amd-gfx@xxxxxxxxxxxxxxxxxxxxx
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=04%7C01%7Clijo.lazar%40amd.com%7C8e117d60de0c4c12bb9b08d89a91b045%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637429297804635030%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=Hymngc63wUytPWZCrmmrKl%2FCdqF067sTlQCbfBNrndA%3D&amp;reserved=0
_______________________________________________
amd-gfx mailing list
amd-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/amd-gfx