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[AMD Official Use Only - Internal Distribution Only]
Acked-by: Alex Deucher <alexander.deucher@xxxxxxx>
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> on behalf of Tao Zhou <tao.zhou1@xxxxxxx>
Sent: Tuesday, November 17, 2020 2:32 AM To: Chen, Jiansong (Simon) <Jiansong.Chen@xxxxxxx>; Gui, Jack <Jack.Gui@xxxxxxx>; Zhang, Hawking <Hawking.Zhang@xxxxxxx>; amd-gfx@xxxxxxxxxxxxxxxxxxxxx <amd-gfx@xxxxxxxxxxxxxxxxxxxxx> Cc: Zhou1, Tao <Tao.Zhou1@xxxxxxx> Subject: [PATCH] drm/amd/pm: support runtime PPTable update for dimgrey_cavefish There is no need to reset DPM for PPTable uploading on
dimgrey_cavefish and PMFW can handle it, same as navy_flounder. Signed-off-by: Tao Zhou <tao.zhou1@xxxxxxx> --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 1904df5a3e20..8e3e7a5bbffe 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -1183,7 +1183,7 @@ static int smu_disable_dpms(struct smu_context *smu) */ if (smu->uploading_custom_pp_table && (adev->asic_type >= CHIP_NAVI10) && - (adev->asic_type <= CHIP_NAVY_FLOUNDER)) + (adev->asic_type <= CHIP_DIMGREY_CAVEFISH)) return 0; /* -- 2.17.1 _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://nam11.safelinks.protection.outlook.com/?url=""> |
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