[PATCH] drm/amd/amdgpu: Update mmio read/write access via debugfs

[Tom St Denis <tom.stdenis@xxxxxxx>]

This patch adds support for wide MMIO addresses (upto 32-bits wide)
at the expense of dropping bank switching support for these addresses.

The patch also moves the PG guard bit to bit 59 which breaks compatibility
with older versions of umr but only if they are running the "--top" command.

Signed-off-by: Tom St Denis <tom.stdenis@xxxxxxx>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 68 +++++++++++----------
 1 file changed, 37 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index 41ca13f0acd5..dd9df90a3bff 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -171,13 +171,14 @@ static void amdgpu_debugfs_autodump_init(struct amdgpu_device *adev)
  * Bit 62:  Indicates a GRBM bank switch is needed
  * Bit 61:  Indicates a SRBM bank switch is needed (implies bit 62 is
  * 	    zero)
+ * Bit 60:  Indicates wide MMIO (32-bit address), disables other features
+ * Bit 59:  Indicates that the PM power gating lock should be held
+ * 	    This is necessary to read registers that might be
+ * 	    unreliable during a power gating transistion.
  * Bits 24..33: The SE or ME selector if needed
  * Bits 34..43: The SH (or SA) or PIPE selector if needed
  * Bits 44..53: The INSTANCE (or CU/WGP) or QUEUE selector if needed
  *
- * Bit 23:  Indicates that the PM power gating lock should be held
- * 	    This is necessary to read registers that might be
- * 	    unreliable during a power gating transistion.
  *
  * The lower bits are the BYTE offset of the register to read.  This
  * allows reading multiple registers in a single call and having
@@ -189,45 +190,50 @@ static int  amdgpu_debugfs_process_reg_op(bool read, struct file *f,
 	struct amdgpu_device *adev = file_inode(f)->i_private;
 	ssize_t result = 0;
 	int r;
-	bool pm_pg_lock, use_bank, use_ring;
+	bool pm_pg_lock, use_bank, use_ring, use_wide;
 	unsigned instance_bank, sh_bank, se_bank, me, pipe, queue, vmid;
 
-	pm_pg_lock = use_bank = use_ring = false;
+	use_wide = pm_pg_lock = use_bank = use_ring = false;
 	instance_bank = sh_bank = se_bank = me = pipe = queue = vmid = 0;
 
 	if (size & 0x3 || *pos & 0x3 ||
 			((*pos & (1ULL << 62)) && (*pos & (1ULL << 61))))
 		return -EINVAL;
 
-	/* are we reading registers for which a PG lock is necessary? */
-	pm_pg_lock = (*pos >> 23) & 1;
-
-	if (*pos & (1ULL << 62)) {
-		se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
-		sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
-		instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
-
-		if (se_bank == 0x3FF)
-			se_bank = 0xFFFFFFFF;
-		if (sh_bank == 0x3FF)
-			sh_bank = 0xFFFFFFFF;
-		if (instance_bank == 0x3FF)
-			instance_bank = 0xFFFFFFFF;
-		use_bank = true;
-	} else if (*pos & (1ULL << 61)) {
-
-		me = (*pos & GENMASK_ULL(33, 24)) >> 24;
-		pipe = (*pos & GENMASK_ULL(43, 34)) >> 34;
-		queue = (*pos & GENMASK_ULL(53, 44)) >> 44;
-		vmid = (*pos & GENMASK_ULL(58, 54)) >> 54;
-
-		use_ring = true;
+	/* is this a wide request? */
+	use_wide = (*pos >> 60) & 1;
+
+	if (!use_wide) {
+		/* are we reading registers for which a PG lock is necessary? */
+		pm_pg_lock = (*pos >> 59) & 1;
+
+		if (*pos & (1ULL << 62)) {
+			se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
+			sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
+			instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
+
+			if (se_bank == 0x3FF)
+				se_bank = 0xFFFFFFFF;
+			if (sh_bank == 0x3FF)
+				sh_bank = 0xFFFFFFFF;
+			if (instance_bank == 0x3FF)
+				instance_bank = 0xFFFFFFFF;
+			use_bank = true;
+		} else if (*pos & (1ULL << 61)) {
+			me = (*pos & GENMASK_ULL(33, 24)) >> 24;
+			pipe = (*pos & GENMASK_ULL(43, 34)) >> 34;
+			queue = (*pos & GENMASK_ULL(53, 44)) >> 44;
+			vmid = (*pos & GENMASK_ULL(58, 54)) >> 54;
+			use_ring = true;
+		} else {
+			use_bank = use_ring = false;
+		}
+
+		*pos &= (1ULL << 22) - 1ULL;
 	} else {
-		use_bank = use_ring = false;
+		*pos &= (1ULL << 32) - 1ULL;
 	}
 
-	*pos &= (1UL << 22) - 1;
-
 	r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
 	if (r < 0) {
 		pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
-- 
2.28.0

_______________________________________________
amd-gfx mailing list
amd-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/amd-gfx