[Why]
Incorrect values were resulting in flash lines
when MPO was enabled and system was left idle.
[How]
Increase min clk values only when MPO is enabled
and display is active to not affect S3 power.
Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@xxxxxxx>
---
.../display/dc/clk_mgr/dcn10/rv1_clk_mgr.c | 35 +++++++++++++++++--
1 file changed, 32 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
index e133edc587d3..c388a003956b 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
@@ -187,6 +187,22 @@ static void ramp_up_dispclk_with_dpp(
clk_mgr->base.clks.max_supported_dppclk_khz = new_clocks->max_supported_dppclk_khz;
}
+static bool is_mpo_enabled(struct dc_state *context)
+{
+ int i;
+
+ for (i = 0; i < context->stream_count; i++) {
+ if (context->stream_status[i].plane_count > 1) {
+ /*
+ * No need to check for all streams as MPO
+ * can be enabled on single stream only for RV.
+ */
+ return true;
+ }
+ }
+ return false;
+}
+
static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
struct dc_state *context,
bool safe_to_lower)
@@ -284,9 +300,22 @@ static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
if (pp_smu->set_hard_min_fclk_by_freq &&
pp_smu->set_hard_min_dcfclk_by_freq &&
pp_smu->set_min_deep_sleep_dcfclk) {
- pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, new_clocks->fclk_khz / 1000);
- pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, new_clocks->dcfclk_khz / 1000);
- pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
+ // Only increase clocks when display is active and MPO is enabled
+ if (display_count && is_mpo_enabled(context)) {
+ pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu,
+ ((new_clocks->fclk_khz / 1000) * 101) / 100);
+ pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu,
+ ((new_clocks->dcfclk_khz / 1000) * 101) / 100);
+ pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu,
+ (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
+ } else {
+ pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu,
+ new_clocks->fclk_khz / 1000);
+ pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu,
+ new_clocks->dcfclk_khz / 1000);
+ pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu,
+ (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
+ }
}
}
}
--
2.17.1
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