Reviewed-by: Nikola Cornij <nikola.cornij@xxxxxxx>
-----Original Message-----
From: Siqueira, Rodrigo <Rodrigo.Siqueira@xxxxxxx>
Sent: Wednesday, October 28, 2020 6:08 PM
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Cornij, Nikola <Nikola.Cornij@xxxxxxx>; Liu, Zhan <Zhan.Liu@xxxxxxx>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@xxxxxxx>; Wentland, Harry <Harry.Wentland@xxxxxxx>; Laktyushkin, Dmytro <Dmytro.Laktyushkin@xxxxxxx>; Park, Chris <Chris.Park@xxxxxxx>
Subject: [PATCH] drm/amd/display: allow 18 bit dp output on DCN3
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@xxxxxxx>
We need this to pass dp compliance.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@xxxxxxx>
Reviewed-by: Chris Park <Chris.Park@xxxxxxx>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@xxxxxxx>
---
.../gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 14 -------------- .../amd/display/dc/dml/dcn30/display_mode_vba_30.c | 2 +-
2 files changed, 1 insertion(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index d1ed2a99bf65..d65496917e93 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -2020,20 +2020,6 @@ static bool dcn30_internal_validate_bw(
dml_log_mode_support_params(&context->bw_ctx.dml);
- /* TODO: Need to check calculated vlevel why that fails validation of below resolutions */
- if (context->res_ctx.pipe_ctx[0].stream != NULL) {
- if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 640 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 480)
- vlevel = 0;
- if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 1280 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 800)
- vlevel = 0;
- if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 1280 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 768)
- vlevel = 0;
- if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 1280 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 1024)
- vlevel = 0;
- if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 2048 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 1536)
- vlevel = 0;
- }
-
if (vlevel == context->bw_ctx.dml.soc.num_states)
goto validate_fail;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
index 9e0ae18e71fa..0f668699809d 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -3628,7 +3628,7 @@ static double TruncToValidBPP(
}
}
} else {
- if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 || DesiredBPP == NonDSCBPP1 || DesiredBPP == NonDSCBPP0)) ||
+ if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 || DesiredBPP
+== NonDSCBPP1 || DesiredBPP == NonDSCBPP0 || DesiredBPP == 18)) ||
(DSCEnable && DesiredBPP >= MinDSCBPP && DesiredBPP <= MaxDSCBPP))) {
return BPP_INVALID;
} else {
--
2.29.1
_______________________________________________
amd-gfx mailing list
amd-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
