[AMD Official Use Only - Internal Distribution Only]
> -----Original Message-----
> From: Alex Deucher <alexdeucher@xxxxxxxxx>
> Sent: Saturday, October 17, 2020 2:10 AM
> To: Liang, Prike <Prike.Liang@xxxxxxx>
> Cc: amd-gfx list <amd-gfx@xxxxxxxxxxxxxxxxxxxxx>; Deucher, Alexander
> <Alexander.Deucher@xxxxxxx>; Huang, Ray <Ray.Huang@xxxxxxx>
> Subject: Re: [PATCH 2/4] drm/amdgpu: add amdgpu_gfx_state_change_set()
> set gfx power change entry
>
> On Fri, Oct 16, 2020 at 5:21 AM Prike Liang <Prike.Liang@xxxxxxx> wrote:
> >
> > The new amdgpu_gfx_state_change_set() funtion can support set GFX
> > power change status to D0/D3.
> >
> > Signed-off-by: Prike Liang <Prike.Liang@xxxxxxx>
> > Acked-by: Huang Rui <ray.huang@xxxxxxx>
> > Reviewed-by: Alex Deucher <alexander.deucher@xxxxxxx>
>
> I presume we'll need something similar for renoir? That can be a follow up
> patch.
[Prike] Yeah, so I have drafted the invoked function amdgpu_gfx_state_change_set() outside of the powerplay driver for common use. But until now haven't checked s0i3 on the Renoir/Cezanne yet and if needed will be implement it in the Renoir SMU driver.
>
> Alex
>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 20
> ++++++++++++++++++++
> > drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 7 +++++++
> > drivers/gpu/drm/amd/include/kgd_pp_interface.h | 1 +
> > drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 20
> ++++++++++++++++++++
> > drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 9 +++++++++
> > drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
> > drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h | 3 ++-
> > 7 files changed, 60 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> > index d612033..e1d6c8a 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> > @@ -789,3 +789,23 @@ void amdgpu_kiq_wreg(struct amdgpu_device
> *adev,
> > uint32_t reg, uint32_t v)
> > failed_kiq_write:
> > pr_err("failed to write reg:%x\n", reg); }
> > +
> > +/* amdgpu_gfx_state_change_set - Handle gfx power state change set
> > + * @adev: amdgpu_device pointer
> > + * @state: gfx power state(1 -eGpuChangeState_D0Entry and 2
> > +-eGpuChangeState_D3Entry)
> > + *
> > + */
> > +
> > +void amdgpu_gfx_state_change_set(struct amdgpu_device *adev, enum
> > +gfx_change_state state) {
> > +
> > + mutex_lock(&adev->pm.mutex);
> > +
> > + if (adev->powerplay.pp_funcs &&
> > + adev->powerplay.pp_funcs->gfx_state_change_set)
> > + ((adev)->powerplay.pp_funcs->gfx_state_change_set(
> > + (adev)->powerplay.pp_handle,
> > + state));
> > +
> > + mutex_unlock(&adev->pm.mutex);
> > +
> > +}
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> > index d43c116..73942b2 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> > @@ -47,6 +47,12 @@ enum gfx_pipe_priority {
> > AMDGPU_GFX_PIPE_PRIO_MAX
> > };
> >
> > +/* Argument for PPSMC_MSG_GpuChangeState */ enum
> gfx_change_state {
> > + GpuChangeState_D0Entry = 1,
> > + GpuChangeState_D3Entry,
> > +};
> > +
> > #define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM 0 #define
> > AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM 15
> >
> > @@ -387,4 +393,5 @@ int amdgpu_gfx_cp_ecc_error_irq(struct
> amdgpu_device *adev,
> > struct amdgpu_iv_entry *entry);
> > uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
> > void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg,
> > uint32_t v);
> > +void amdgpu_gfx_state_change_set(struct amdgpu_device *adev, enum
> > +gfx_change_state state);
> > #endif
> > diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> > b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> > index a7f92d0..e7b69dd 100644
> > --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> > +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> > @@ -284,6 +284,7 @@ struct amd_pm_funcs {
> > int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input,
> uint32_t size);
> > int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state);
> > int (*smu_i2c_bus_access)(void *handle, bool acquire);
> > + int (*gfx_state_change_set)(void *handle, uint32_t state);
> > /* export to DC */
> > u32 (*get_sclk)(void *handle, bool low);
> > u32 (*get_mclk)(void *handle, bool low); diff --git
> > a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> > b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> > index 7e6dcdf..4f319be 100644
> > --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> > +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> > @@ -1321,6 +1321,25 @@ static int pp_set_powergating_by_smu(void
> *handle,
> > return ret;
> > }
> >
> > +static int pp_gfx_state_change_set(void *handle, uint32_t state) {
> > + struct pp_hwmgr *hwmgr = handle;
> > +
> > + if (!hwmgr || !hwmgr->pm_en)
> > + return -EINVAL;
> > +
> > + if (hwmgr->hwmgr_func->gfx_state_change == NULL) {
> > + pr_info_ratelimited("%s was not implemented.\n", __func__);
> > + return -EINVAL;
> > + }
> > +
> > + mutex_lock(&hwmgr->smu_lock);
> > + hwmgr->hwmgr_func->gfx_state_change(hwmgr, state);
> > + mutex_unlock(&hwmgr->smu_lock);
> > +
> > + return 0;
> > +}
> > +
> > static int pp_notify_smu_enable_pwe(void *handle) {
> > struct pp_hwmgr *hwmgr = handle; @@ -1625,6 +1644,7 @@ static
> > const struct amd_pm_funcs pp_dpm_funcs = {
> > .switch_power_profile = pp_dpm_switch_power_profile,
> > .set_clockgating_by_smu = pp_set_clockgating_by_smu,
> > .set_powergating_by_smu = pp_set_powergating_by_smu,
> > + .gfx_state_change_set = pp_gfx_state_change_set,
> > .get_power_profile_mode = pp_get_power_profile_mode,
> > .set_power_profile_mode = pp_set_power_profile_mode,
> > .odn_edit_dpm_table = pp_odn_edit_dpm_table, diff --git
> > a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> > b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> > index c9cfe90..3f354da 100644
> > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> > @@ -319,6 +319,14 @@ static bool smu10_is_gfx_on(struct pp_hwmgr
> *hwmgr)
> > return false;
> > }
> >
> > +static int smu10_gfx_state_change(struct pp_hwmgr *hwmgr, uint32_t
> > +state) {
> > + struct amdgpu_device *adev = hwmgr->adev;
> > + smum_send_msg_to_smc_with_parameter(hwmgr,
> > +PPSMC_MSG_GpuChangeState, state, NULL);
> > +
> > + return 0;
> > +}
> > +
> > static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr) {
> > struct amdgpu_device *adev = hwmgr->adev; @@ -1394,6 +1402,7
> > @@ static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
> > .get_power_profile_mode = smu10_get_power_profile_mode,
> > .set_power_profile_mode = smu10_set_power_profile_mode,
> > .asic_reset = smu10_asic_reset,
> > + .gfx_state_change = smu10_gfx_state_change,
> > };
> >
> > int smu10_init_function_pointers(struct pp_hwmgr *hwmgr) diff --git
> > a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> > b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> > index 15ed6cb..2c9580b 100644
> > --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> > +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> > @@ -359,6 +359,7 @@ struct pp_hwmgr_func {
> > int (*set_xgmi_pstate)(struct pp_hwmgr *hwmgr, uint32_t pstate);
> > int (*disable_power_features_for_compute_performance)(struct
> pp_hwmgr *hwmgr,
> > bool disable);
> > + int (*gfx_state_change)(struct pp_hwmgr *hwmgr, uint32_t
> > + state);
> > };
> >
> > struct pp_table_func {
> > diff --git a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
> > b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
> > index df4677d..4c7e08b 100644
> > --- a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
> > +++ b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
> > @@ -83,7 +83,8 @@
> > #define PPSMC_MSG_SetSoftMaxVcn 0x34
> > #define PPSMC_MSG_PowerGateMmHub 0x35
> > #define PPSMC_MSG_SetRccPfcPmeRestoreRegister 0x36
> > -#define PPSMC_Message_Count 0x37
> > +#define PPSMC_MSG_GpuChangeState 0x37
> > +#define PPSMC_Message_Count 0x42
> >
> > typedef uint16_t PPSMC_Result;
> > typedef int PPSMC_Msg;
> > --
> > 2.7.4
> >
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