Am 2020-10-16 um 11:34 a.m. schrieb Nirmoy Das:
> Compute queues are configurable with module param, num_kcq.
> amdgpu_gfx_is_high_priority_compute_queue was setting 1st 4 queues to
> high priority queue leaving a null drm scheduler in
> adev->gpu_sched[hw_ip]["normal_prio"].sched if num_kcq < 5
>
> Fixes: 33abcb1f5a1719b1c (drm/amdgpu: set compute queue priority at mqd_init)
>
> Signed-off-by: Nirmoy Das <nirmoy.das@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
> 5 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index 8c9bacfdbc30..56d384656c45 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -193,10 +193,10 @@ static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev)
> }
>
> bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
> - int queue)
> + int pipe)
> {
> - /* Policy: make queue 0 of each pipe as high priority compute queue */
> - return (queue == 0);
> + /* Policy: even pipe num = normal priority, odd pipe num = high priority */
> + return ((pipe % 2) != 0);
I think this will break on systems where multipipe_policy is false. If
all KCQs are on the same pipe, you'll end up without any high-priority
queues.
Regards,
Felix
>
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> index 190753930b11..b167ebb6385d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> @@ -374,7 +374,7 @@ void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
> bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
> int pipe, int queue);
> bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
> - int queue);
> + int pipe);
> int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
> int pipe, int queue);
> void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index e42542e564f7..e39737680017 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -4465,7 +4465,7 @@ static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
> irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
> + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
> + ring->pipe;
> - hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue) ?
> + hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe) ?
> AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
> /* type-2 packets are deprecated on MEC, use type-3 instead */
> r = amdgpu_ring_init(adev, ring, 1024,
> @@ -6498,7 +6498,7 @@ static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct
> struct amdgpu_device *adev = ring->adev;
>
> if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
> - if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) {
> + if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe)) {
> mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
> mqd->cp_hqd_queue_priority =
> AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index d5843e8a6e17..ada54a96c676 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -1915,7 +1915,7 @@ static int gfx_v8_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
> + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
> + ring->pipe;
>
> - hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue) ?
> + hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe) ?
> AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_RING_PRIO_DEFAULT;
> /* type-2 packets are deprecated on MEC, use type-3 instead */
> r = amdgpu_ring_init(adev, ring, 1024,
> @@ -4433,7 +4433,7 @@ static void gfx_v8_0_mqd_set_priority(struct amdgpu_ring *ring, struct vi_mqd *m
> struct amdgpu_device *adev = ring->adev;
>
> if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
> - if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) {
> + if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe)) {
> mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
> mqd->cp_hqd_queue_priority =
> AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 0d8e203b10ef..94cfaeebb7d1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -2228,7 +2228,7 @@ static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
> irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
> + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
> + ring->pipe;
> - hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue) ?
> + hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe) ?
> AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
> /* type-2 packets are deprecated on MEC, use type-3 instead */
> return amdgpu_ring_init(adev, ring, 1024,
> @@ -3383,7 +3383,7 @@ static void gfx_v9_0_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *m
> struct amdgpu_device *adev = ring->adev;
>
> if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
> - if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) {
> + if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe)) {
> mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
> mqd->cp_hqd_queue_priority =
> AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
> --
> 2.28.0
>
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