Correct powertune table setup for Polaris.
Change-Id: I31fa01c5e5f88233616e51966b4fb5a161e35ff0
Signed-off-by: Evan Quan <evan.quan@xxxxxxx>
Acked-by: Alex Deucher <alexander.deucher@xxxxxxx>
---
drivers/gpu/drm/amd/pm/inc/hwmgr.h | 1 +
.../drm/amd/pm/powerplay/hwmgr/pptable_v1_0.h | 36 ++++++++++++++
.../powerplay/hwmgr/process_pptables_v1_0.c | 49 ++++++++++++++++++-
3 files changed, 85 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/hwmgr.h b/drivers/gpu/drm/amd/pm/inc/hwmgr.h
index dad703ba0522..0e4707a76f6d 100644
--- a/drivers/gpu/drm/amd/pm/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/pm/inc/hwmgr.h
@@ -441,6 +441,7 @@ struct phm_cac_tdp_table {
uint8_t ucPlx_I2C_Line;
uint32_t usBoostPowerLimit;
uint8_t ucCKS_LDO_REFSEL;
+ uint8_t ucHotSpotOnly;
};
struct phm_tdp_table {
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/pptable_v1_0.h b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/pptable_v1_0.h
index 614f61ae214a..b0ac4d121adc 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/pptable_v1_0.h
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/pptable_v1_0.h
@@ -419,6 +419,42 @@ typedef struct _ATOM_Fiji_PowerTune_Table {
USHORT usReserved;
} ATOM_Fiji_PowerTune_Table;
+typedef struct _ATOM_Polaris_PowerTune_Table
+{
+ UCHAR ucRevId;
+ USHORT usTDP;
+ USHORT usConfigurableTDP;
+ USHORT usTDC;
+ USHORT usBatteryPowerLimit;
+ USHORT usSmallPowerLimit;
+ USHORT usLowCACLeakage;
+ USHORT usHighCACLeakage;
+ USHORT usMaximumPowerDeliveryLimit;
+ USHORT usTjMax; // For Fiji, this is also usTemperatureLimitEdge;
+ USHORT usPowerTuneDataSetID;
+ USHORT usEDCLimit;
+ USHORT usSoftwareShutdownTemp;
+ USHORT usClockStretchAmount;
+ USHORT usTemperatureLimitHotspot; //The following are added for Fiji
+ USHORT usTemperatureLimitLiquid1;
+ USHORT usTemperatureLimitLiquid2;
+ USHORT usTemperatureLimitVrVddc;
+ USHORT usTemperatureLimitVrMvdd;
+ USHORT usTemperatureLimitPlx;
+ UCHAR ucLiquid1_I2C_address; //Liquid
+ UCHAR ucLiquid2_I2C_address;
+ UCHAR ucLiquid_I2C_Line;
+ UCHAR ucVr_I2C_address; //VR
+ UCHAR ucVr_I2C_Line;
+ UCHAR ucPlx_I2C_address; //PLX
+ UCHAR ucPlx_I2C_Line;
+ USHORT usBoostPowerLimit;
+ UCHAR ucCKS_LDO_REFSEL;
+ UCHAR ucHotSpotOnly;
+ UCHAR ucReserve;
+ USHORT usReserve;
+} ATOM_Polaris_PowerTune_Table;
+
#define ATOM_PPM_A_A 1
#define ATOM_PPM_A_I 2
typedef struct _ATOM_Tonga_PPM_Table {
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c
index 4ed9f8106b2e..801a56502670 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c
@@ -613,7 +613,7 @@ static int get_cac_tdp_table(
le16_to_cpu(tonga_table->usSoftwareShutdownTemp);
tdp_table->usClockStretchAmount =
le16_to_cpu(tonga_table->usClockStretchAmount);
- } else { /* Fiji and newer */
+ } else if (table->ucRevId < 4) { /* Fiji and newer */
const ATOM_Fiji_PowerTune_Table *fijitable =
(ATOM_Fiji_PowerTune_Table *)table;
tdp_table->usTDP = le16_to_cpu(fijitable->usTDP);
@@ -657,6 +657,53 @@ static int get_cac_tdp_table(
tdp_table->ucVr_I2C_Line = fijitable->ucVr_I2C_Line;
tdp_table->ucPlx_I2C_address = fijitable->ucPlx_I2C_address;
tdp_table->ucPlx_I2C_Line = fijitable->ucPlx_I2C_Line;
+ } else {
+ const ATOM_Polaris_PowerTune_Table *polaristable =
+ (ATOM_Polaris_PowerTune_Table *)table;
+ tdp_table->usTDP = le16_to_cpu(polaristable->usTDP);
+ tdp_table->usConfigurableTDP = le16_to_cpu(polaristable->usConfigurableTDP);
+ tdp_table->usTDC = le16_to_cpu(polaristable->usTDC);
+ tdp_table->usBatteryPowerLimit = le16_to_cpu(polaristable->usBatteryPowerLimit);
+ tdp_table->usSmallPowerLimit = le16_to_cpu(polaristable->usSmallPowerLimit);
+ tdp_table->usLowCACLeakage = le16_to_cpu(polaristable->usLowCACLeakage);
+ tdp_table->usHighCACLeakage = le16_to_cpu(polaristable->usHighCACLeakage);
+ tdp_table->usMaximumPowerDeliveryLimit =
+ le16_to_cpu(polaristable->usMaximumPowerDeliveryLimit);
+ tdp_table->usDefaultTargetOperatingTemp =
+ le16_to_cpu(polaristable->usTjMax);
+ tdp_table->usTargetOperatingTemp =
+ le16_to_cpu(polaristable->usTjMax); /*Set the initial temp to the same as default */
+ tdp_table->usPowerTuneDataSetID =
+ le16_to_cpu(polaristable->usPowerTuneDataSetID);
+ tdp_table->usSoftwareShutdownTemp =
+ le16_to_cpu(polaristable->usSoftwareShutdownTemp);
+ tdp_table->usClockStretchAmount =
+ le16_to_cpu(polaristable->usClockStretchAmount);
+ tdp_table->usTemperatureLimitHotspot =
+ le16_to_cpu(polaristable->usTemperatureLimitHotspot);
+ tdp_table->usTemperatureLimitLiquid1 =
+ le16_to_cpu(polaristable->usTemperatureLimitLiquid1);
+ tdp_table->usTemperatureLimitLiquid2 =
+ le16_to_cpu(polaristable->usTemperatureLimitLiquid2);
+ tdp_table->usTemperatureLimitVrVddc =
+ le16_to_cpu(polaristable->usTemperatureLimitVrVddc);
+ tdp_table->usTemperatureLimitVrMvdd =
+ le16_to_cpu(polaristable->usTemperatureLimitVrMvdd);
+ tdp_table->usTemperatureLimitPlx =
+ le16_to_cpu(polaristable->usTemperatureLimitPlx);
+ tdp_table->ucLiquid1_I2C_address =
+ polaristable->ucLiquid1_I2C_address;
+ tdp_table->ucLiquid2_I2C_address =
+ polaristable->ucLiquid2_I2C_address;
+ tdp_table->ucLiquid_I2C_Line =
+ polaristable->ucLiquid_I2C_Line;
+ tdp_table->ucVr_I2C_address = polaristable->ucVr_I2C_address;
+ tdp_table->ucVr_I2C_Line = polaristable->ucVr_I2C_Line;
+ tdp_table->ucPlx_I2C_address = polaristable->ucPlx_I2C_address;
+ tdp_table->ucPlx_I2C_Line = polaristable->ucPlx_I2C_Line;
+ tdp_table->usBoostPowerLimit = polaristable->usBoostPowerLimit;
+ tdp_table->ucCKS_LDO_REFSEL = polaristable->ucCKS_LDO_REFSEL;
+ tdp_table->ucHotSpotOnly = polaristable->ucHotSpotOnly;
}
*cac_tdp_table = tdp_table;
--
2.28.0
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