[AMD Official Use Only - Internal Distribution Only]
Hi Alex,
It was intended to align with other ASICs. The output for this on Arcturus is:
0: 8.0GT/s, x16 618Mhz *
Is not that OK?
BR
Evan
-----Original Message-----
From: Alex Deucher <alexdeucher@xxxxxxxxx>
Sent: Wednesday, October 14, 2020 9:18 PM
To: Quan, Evan <Evan.Quan@xxxxxxx>
Cc: amd-gfx list <amd-gfx@xxxxxxxxxxxxxxxxxxxxx>; Deucher, Alexander <Alexander.Deucher@xxxxxxx>
Subject: Re: [PATCH 2/2] drm/amd/pm: populate Arcturus PCIE link state
On Wed, Oct 14, 2020 at 1:21 AM Evan Quan <evan.quan@xxxxxxx> wrote:
>
> Populate current link speed, width and clock domain frequency.
>
> Change-Id: Ic342fbd8f5e2495d212eaa4b85b4e146838e0525
> Signed-off-by: Evan Quan <evan.quan@xxxxxxx>
> ---
> drivers/gpu/drm/amd/pm/amdgpu_pm.c | 3 ---
> .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 18
> ++++++++++++++++++
> 2 files changed, 18 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> index 46eea3f8f958..f87411cfa4da 100644
> --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> @@ -2124,9 +2124,6 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_
> } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
> if (asic_type < CHIP_VEGA20)
> *states = ATTR_STATE_UNSUPPORTED;
> - } else if (DEVICE_ATTR_IS(pp_dpm_pcie)) {
> - if (asic_type == CHIP_ARCTURUS)
> - *states = ATTR_STATE_UNSUPPORTED;
> } else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
> *states = ATTR_STATE_UNSUPPORTED;
> if ((is_support_sw_smu(adev) && adev->smu.od_enabled)
> || diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> index f982b9090d7b..46d950757230 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> @@ -720,6 +720,7 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
> struct smu_11_0_dpm_table *single_dpm_table;
> struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
> struct smu_11_0_dpm_context *dpm_context = NULL;
> + uint32_t gen_speed, lane_width;
>
> if (amdgpu_ras_intr_triggered())
> return snprintf(buf, PAGE_SIZE, "unavailable\n"); @@
> -823,6 +824,23 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
> now) ? "*" : ""));
> break;
>
> + case SMU_PCIE:
> + gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
> + lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
> + size += sprintf(buf + size, "0: %s %s %dMhz *\n",
> + (gen_speed == 0) ? "2.5GT/s," :
> + (gen_speed == 1) ? "5.0GT/s," :
> + (gen_speed == 2) ? "8.0GT/s," :
> + (gen_speed == 3) ? "16.0GT/s," : "",
> + (lane_width == 1) ? "x1" :
> + (lane_width == 2) ? "x2" :
> + (lane_width == 3) ? "x4" :
> + (lane_width == 4) ? "x8" :
> + (lane_width == 5) ? "x12" :
> + (lane_width == 6) ? "x16" : "",
> + smu->smu_table.boot_values.lclk /
> + 100);
We should put a * by the link speed for consistency with other asics.
Alex
> + break;
> +
> default:
> break;
> }
> --
> 2.28.0
>
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