From: Huang Rui <ray.huang@xxxxxxx>
This patch is to add power gating handle for gfx10.
Signed-off-by: Huang Rui <ray.huang@xxxxxxx>
Acked-by: Alex Deucher <alexander.deucher@xxxxxxx>
Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 27 ++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index fd29a6d7285b..f2849f180c91 100755
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -7583,6 +7583,30 @@ static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offse
return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
}
+static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
+{
+ int data;
+
+ if (enable && (adev->cg_flags & AMD_PG_SUPPORT_GFX_PG)) {
+ data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
+ data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
+ WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
+ } else {
+ data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
+ data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
+ WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
+ }
+}
+
+static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
+{
+ amdgpu_gfx_rlc_enter_safe_mode(adev);
+
+ gfx_v10_cntl_power_gating(adev, enable);
+
+ amdgpu_gfx_rlc_exit_safe_mode(adev);
+}
+
static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
.is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
.set_safe_mode = gfx_v10_0_set_safe_mode,
@@ -7630,6 +7654,9 @@ static int gfx_v10_0_set_powergating_state(void *handle,
case CHIP_NAVY_FLOUNDER:
amdgpu_gfx_off_ctrl(adev, enable);
break;
+ case CHIP_VANGOGH:
+ gfx_v10_cntl_pg(adev, enable);
+ break;
default:
break;
}
--
2.25.4
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