Applied with a slight cleanup to the commit message.
Thanks!
Alex
On Thu, Sep 17, 2020 at 3:33 AM Mauro Rossi <issor.oruam@xxxxxxxxx> wrote:
>
> (v1) Changelog
>
> [Why]
> After commit c69dd2d "drm/amd/display: Refactor clk_mgr functions"
> dc/clk_mgr requires these changes to add SI parts support
> Necessary to avoid hitting default: ASSERT(0); /* Unknown Asic */
> that would cause kernel freeze
>
> [How]
> Add case statement for FAMILY_SI chipsets
>
> (v2) Changelog
>
> [Why]
> DCE6 has no DPREFCLK_CNTL register
>
> [How]
> Add DCE6 specific macros definitions for CLK registers and masks
> Add DCE6 specific dce60/dce60_clk_mgr.c for DCE6 customization
> Code style: reuse all the public functions in dce100/dce_clk_mgr.h header
> Code style: use dce60_* static functions as per other DCE implementations
> Add dce60_get_dp_ref_freq_khz() w/o using DPREFCLK_CNTL register
> Use dce60_get_dp_ref_freq_khz() function in dce60_funcs
> Add DCE6 specific dce60_clk_mgr_construct
> dc/clk_mgr/dce_clk_mgr.c: use dce60_clk_mgr_construct for FAMILY_SI chipsets
> Add Makefile rules for dce60_clk_mgr.o target conditional to CONFIG_DRM_AMD_DC_SI
>
> (v3) Changelog
>
> [Why]
> linux-next kernel test robot reported the following problem:
> warning: no previous prototype for 'dce60_get_dp_ref_freq_khz' [-Wmissing-prototypes]
>
> [How]
> mark dce60_get_dp_ref_freq_khz() as static
>
> Fixes: 3ecb3b794e2 "drm/amd/display: dc/clk_mgr: add support for SI parts (v2)"
> Reported-by: kernel test robot <lkp@xxxxxxxxx>
> Signed-off-by: Mauro Rossi <issor.oruam@xxxxxxxxx>
> ---
> drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
> index c11c6b3a787d..0267644717b2 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
> @@ -80,7 +80,7 @@ static const struct state_dependent_clocks dce60_max_clks_by_state[] = {
> /* ClocksStatePerformance */
> { .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
>
> -int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
> +static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
> {
> struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
> int dprefclk_wdivider;
> --
> 2.25.1
>
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