[AMD Public Use] You want to call it in SRIOV case or in bare-metal case? Regards, Guchun -----Original Message----- From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Jingwen Chen Sent: Thursday, September 17, 2020 5:17 PM To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx Cc: Chen, JingWen <JingWen.Chen2@xxxxxxx> Subject: [PATCH] drm/amd/pm: Skip smu_post_init in SRIOV smu_post_init needs to enable SMU feature, while this require virtualization off. Skip it since this feature is not used in SRIOV. v2: move the check to the early stage of smu_post_init. Signed-off-by: Jingwen Chen <Jingwen.Chen2@xxxxxxx> --- drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c index a027c7fdad56..a950f009c794 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c @@ -2631,6 +2631,9 @@ static int navi10_post_smu_init(struct smu_context *smu) uint64_t feature_mask = 0; int ret = 0; + if (!amdgpu_sriov_vf(adev)) + return 0; + /* For Naiv1x, enable these features only after DAL initialization */ if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK) feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); -- 2.25.1 _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cguchun.chen%40amd.com%7C12ec63de0caa4134415008d85aea7b6a%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637359310721844702&sdata=9JCzyhqPIKMZV%2BBEL83HZyfwCyZjTP5iPgs7Hn4Epx8%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx
