[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Kenneth Feng <kenneth.feng@xxxxxxx>
-----Original Message-----
From: Jiansong Chen <Jiansong.Chen@xxxxxxx>
Sent: Monday, September 14, 2020 4:10 PM
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Zhou1, Tao <Tao.Zhou1@xxxxxxx>; Feng, Kenneth <Kenneth.Feng@xxxxxxx>; Quan, Evan <Evan.Quan@xxxxxxx>; Chen, Jiansong (Simon) <Jiansong.Chen@xxxxxxx>
Subject: [PATCH] drm/amd/pm: support runtime pptable update for sienna_cichlid etc.
This avoids smu issue when enabling runtime pptable update for sienna_cichlid and so on. Runtime pptable udpate is needed for test and debug purpose.
Signed-off-by: Jiansong Chen <Jiansong.Chen@xxxxxxx>
Change-Id: I70b704ab4d6efd169f579c392e5dbc2737dc1fb2
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 7a55ece1f124..7618f9972b8c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1129,7 +1129,7 @@ static int smu_disable_dpms(struct smu_context *smu)
*/
if (smu->uploading_custom_pp_table &&
(adev->asic_type >= CHIP_NAVI10) &&
- (adev->asic_type <= CHIP_NAVI12))
+ (adev->asic_type <= CHIP_NAVY_FLOUNDER))
return 0;
/*
@@ -1214,7 +1214,9 @@ static int smu_hw_fini(void *handle) int smu_reset(struct smu_context *smu) {
struct amdgpu_device *adev = smu->adev;
- int ret = 0;
+ int ret;
+
+ amdgpu_gfx_off_ctrl(smu->adev, false);
ret = smu_hw_fini(adev);
if (ret)
@@ -1225,8 +1227,12 @@ int smu_reset(struct smu_context *smu)
return ret;
ret = smu_late_init(adev);
+ if (ret)
+ return ret;
- return ret;
+ amdgpu_gfx_off_ctrl(smu->adev, true);
+
+ return 0;
}
static int smu_suspend(void *handle)
--
2.25.1
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