RE: [PATCH] drm/amd/pm: fix is_dpm_running() run error on 32bit system

["Chen, Jiansong (Simon)" <Jiansong.Chen@xxxxxxx>]

[AMD Official Use Only - Internal Distribution Only]

Good point, but  I wonder whether the outmost uint64_t cast is necessary?

Regards,
Jiansong
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Kevin
Sent: Monday, August 24, 2020 4:59 PM
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Huang, Ray <Ray.Huang@xxxxxxx>; Wang, Kevin(Yang) <Kevin1.Wang@xxxxxxx>
Subject: [PATCH] drm/amd/pm: fix is_dpm_running() run error on 32bit system

From: Kevin Wang <kevin1.wang@xxxxxxx>

the C type "unsigned long" size is 32bit on 32bit system, it will cause code logic error, so replace it with "uint64_t".

Signed-off-by: Kevin <kevin1.wang@xxxxxxx>
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c       | 9 +++++++--
 drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c         | 9 +++++++--
 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 9 +++++++--
 3 files changed, 21 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index 8347b1f2509f..e619315b0f5c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -1844,10 +1844,15 @@ static bool arcturus_is_dpm_running(struct smu_context *smu)  {
 int ret = 0;
 uint32_t feature_mask[2];
-unsigned long feature_enabled;
+uint64_t feature_enabled;
+
 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
-feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
+if (ret)
+return false;
+
+feature_enabled = (uint64_t)((uint64_t)feature_mask[0] |
    ((uint64_t)feature_mask[1] << 32));
+
 return !!(feature_enabled & SMC_DPM_FEATURE);  }

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 72f3d68691d8..d95b370adaf4 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -1345,10 +1345,15 @@ static bool navi10_is_dpm_running(struct smu_context *smu)  {
 int ret = 0;
 uint32_t feature_mask[2];
-unsigned long feature_enabled;
+uint64_t feature_enabled;
+
 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
-feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
+if (ret)
+return false;
+
+feature_enabled = (uint64_t)((uint64_t)feature_mask[0] |
    ((uint64_t)feature_mask[1] << 32));
+
 return !!(feature_enabled & SMC_DPM_FEATURE);  }

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 66d655958a78..f8df6448ab4d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -1150,10 +1150,15 @@ static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)  {
 int ret = 0;
 uint32_t feature_mask[2];
-unsigned long feature_enabled;
+uint64_t feature_enabled;
+
 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
-feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
+if (ret)
+return false;
+
+feature_enabled = (uint64_t)((uint64_t)feature_mask[0] |
    ((uint64_t)feature_mask[1] << 32));
+
 return !!(feature_enabled & SMC_DPM_FEATURE);  }

--
2.27.0

_______________________________________________
amd-gfx mailing list
amd-gfx@xxxxxxxxxxxxxxxxxxxxx
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=02%7C01%7CJiansong.Chen%40amd.com%7Cffe808387ca14e51bab408d8480bc717%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637338562729795065&amp;sdata=U2xw6nM06S0Am3TFYfyLhCHob2k3UH%2BYgMX1hYFKKHE%3D&amp;reserved=0
_______________________________________________
amd-gfx mailing list
amd-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/amd-gfx