On Wed, Aug 19, 2020 at 5:58 AM Evan Quan <evan.quan@xxxxxxx> wrote:
>
> For entering UMD stable Pstate, the operations to enter rlc_safe
> mode, disable mgcg_perfmon and disable PCIE aspm are needed. And
> the opposite operations should be performed on UMD stable Pstate
> exiting.
>
> Change-Id: Iff4aa465fd16f55a4f4de8ee0503997b204f8f9d
> Signed-off-by: Evan Quan <evan.quan@xxxxxxx>
Might want to add stub callbacks for si.c, cik.c, vi.c as well to
avoid unwanted crashes if this ends up getting used elsewhere.
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +++
> drivers/gpu/drm/amd/amdgpu/nv.c | 7 +++++++
> drivers/gpu/drm/amd/amdgpu/soc15.c | 7 +++++++
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 ++
> 4 files changed, 19 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 8ba389780001..6ff4ddb09d1f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -617,6 +617,8 @@ struct amdgpu_asic_funcs {
> uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
> /* device supports BACO */
> bool (*supports_baco)(struct amdgpu_device *adev);
> + /* enter/exit umd stable pstate */
> + int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);
> };
>
> /*
> @@ -1132,6 +1134,7 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
> #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
> #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
> #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
> +#define amdgpu_asic_update_umd_stable_pstate(adev, enter) (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter))
>
> #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
> index 54e941e0db60..d07c84a7543d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> @@ -691,6 +691,12 @@ static void nv_init_doorbell_index(struct amdgpu_device *adev)
> adev->doorbell_index.sdma_doorbell_range = 20;
> }
>
> +static int nv_update_umd_stable_pstate(struct amdgpu_device *adev,
> + bool enter)
> +{
> + return 0;
> +}
> +
> static const struct amdgpu_asic_funcs nv_asic_funcs =
> {
> .read_disabled_bios = &nv_read_disabled_bios,
> @@ -710,6 +716,7 @@ static const struct amdgpu_asic_funcs nv_asic_funcs =
> .need_reset_on_init = &nv_need_reset_on_init,
> .get_pcie_replay_count = &nv_get_pcie_replay_count,
> .supports_baco = &nv_asic_supports_baco,
> + .update_umd_stable_pstate = &nv_update_umd_stable_pstate,
> };
>
> static int nv_common_early_init(void *handle)
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 3cd98c144bc6..d9671db3b98d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -1029,6 +1029,12 @@ static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
> return (nak_r + nak_g);
> }
>
> +static int soc15_update_umd_stable_pstate(struct amdgpu_device *adev,
> + bool enter)
> +{
> + return 0;
> +}
> +
> static const struct amdgpu_asic_funcs soc15_asic_funcs =
> {
> .read_disabled_bios = &soc15_read_disabled_bios,
> @@ -1049,6 +1055,7 @@ static const struct amdgpu_asic_funcs soc15_asic_funcs =
> .need_reset_on_init = &soc15_need_reset_on_init,
> .get_pcie_replay_count = &soc15_get_pcie_replay_count,
> .supports_baco = &soc15_supports_baco,
> + .update_umd_stable_pstate = &soc15_update_umd_stable_pstate,
> };
>
> static const struct amdgpu_asic_funcs vega20_asic_funcs =
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index 8eb5b92903cd..db0f1718087d 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -1442,6 +1442,7 @@ static int smu_enable_umd_pstate(void *handle,
> AMD_CG_STATE_UNGATE);
> smu_gfx_ulv_control(smu, false);
> smu_deep_sleep_control(smu, false);
> + amdgpu_asic_update_umd_stable_pstate(smu->adev, true);
> }
> } else {
> /* exit umd pstate, restore level, enable gfx cg*/
> @@ -1449,6 +1450,7 @@ static int smu_enable_umd_pstate(void *handle,
> if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
> *level = smu_dpm_ctx->saved_dpm_level;
> smu_dpm_ctx->enable_umd_pstate = false;
> + amdgpu_asic_update_umd_stable_pstate(smu->adev, false);
> smu_deep_sleep_control(smu, true);
> smu_gfx_ulv_control(smu, true);
> amdgpu_device_ip_set_clockgating_state(smu->adev,
> --
> 2.28.0
>
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