Considering the same logic can be applied to Arcturus, Navi1X and Sienna Cichlid. Change-Id: I9b80956fee5b094ea0e102601add6c02e3429719 Signed-off-by: Evan Quan <evan.quan@xxxxxxx> --- drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 3 ++ .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 35 +------------------ .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 35 +------------------ .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 35 +------------------ .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 33 +++++++++++++++++ 5 files changed, 39 insertions(+), 102 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h index 89d70165ac44..1c9464826ff7 100644 --- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h +++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h @@ -277,5 +277,8 @@ void smu_v11_0_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics); int smu_v11_0_gfx_ulv_control(struct smu_context *smu, bool enablement); +int smu_v11_0_deep_sleep_control(struct smu_context *smu, + bool enablement); + #endif #endif diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c index 81b584abeea2..8347b1f2509f 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c @@ -2313,39 +2313,6 @@ static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu, return sizeof(struct gpu_metrics_v1_0); } -static int arcturus_deep_sleep_control(struct smu_context *smu, - bool enablement) -{ - struct amdgpu_device *adev = smu->adev; - int ret = 0; - - if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) { - ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement); - if (ret) { - dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable"); - return ret; - } - } - - if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) { - ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement); - if (ret) { - dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable"); - return ret; - } - } - - if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) { - ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement); - if (ret) { - dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable"); - return ret; - } - } - - return ret; -} - static const struct pptable_funcs arcturus_ppt_funcs = { /* init dpm */ .get_allowed_feature_mask = arcturus_get_allowed_feature_mask, @@ -2425,7 +2392,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = { .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, .get_gpu_metrics = arcturus_get_gpu_metrics, .gfx_ulv_control = smu_v11_0_gfx_ulv_control, - .deep_sleep_control = arcturus_deep_sleep_control, + .deep_sleep_control = smu_v11_0_deep_sleep_control, }; void arcturus_set_ppt_funcs(struct smu_context *smu) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c index ddb693888d64..72f3d68691d8 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c @@ -2578,39 +2578,6 @@ static int navi10_enable_mgpu_fan_boost(struct smu_context *smu) NULL); } -static int navi10_deep_sleep_control(struct smu_context *smu, - bool enablement) -{ - struct amdgpu_device *adev = smu->adev; - int ret = 0; - - if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) { - ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement); - if (ret) { - dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable"); - return ret; - } - } - - if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) { - ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement); - if (ret) { - dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable"); - return ret; - } - } - - if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) { - ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement); - if (ret) { - dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable"); - return ret; - } - } - - return ret; -} - static const struct pptable_funcs navi10_ppt_funcs = { .get_allowed_feature_mask = navi10_get_allowed_feature_mask, .set_default_dpm_table = navi10_set_default_dpm_table, @@ -2694,7 +2661,7 @@ static const struct pptable_funcs navi10_ppt_funcs = { .get_gpu_metrics = navi10_get_gpu_metrics, .enable_mgpu_fan_boost = navi10_enable_mgpu_fan_boost, .gfx_ulv_control = smu_v11_0_gfx_ulv_control, - .deep_sleep_control = navi10_deep_sleep_control, + .deep_sleep_control = smu_v11_0_deep_sleep_control, }; void navi10_set_ppt_funcs(struct smu_context *smu) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index b2ad6a5f6728..8ffa8b71b75f 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -2718,39 +2718,6 @@ static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu) NULL); } -static int sienna_cichlid_deep_sleep_control(struct smu_context *smu, - bool enablement) -{ - struct amdgpu_device *adev = smu->adev; - int ret = 0; - - if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) { - ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement); - if (ret) { - dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable"); - return ret; - } - } - - if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) { - ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement); - if (ret) { - dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable"); - return ret; - } - } - - if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) { - ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement); - if (ret) { - dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable"); - return ret; - } - } - - return ret; -} - static const struct pptable_funcs sienna_cichlid_ppt_funcs = { .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask, .set_default_dpm_table = sienna_cichlid_set_default_dpm_table, @@ -2830,7 +2797,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = { .get_gpu_metrics = sienna_cichlid_get_gpu_metrics, .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost, .gfx_ulv_control = smu_v11_0_gfx_ulv_control, - .deep_sleep_control = sienna_cichlid_deep_sleep_control, + .deep_sleep_control = smu_v11_0_deep_sleep_control, }; void sienna_cichlid_set_ppt_funcs(struct smu_context *smu) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c index f1130a288f1d..548db1edd352 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c @@ -1996,3 +1996,36 @@ int smu_v11_0_gfx_ulv_control(struct smu_context *smu, return ret; } + +int smu_v11_0_deep_sleep_control(struct smu_context *smu, + bool enablement) +{ + struct amdgpu_device *adev = smu->adev; + int ret = 0; + + if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) { + ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement); + if (ret) { + dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable"); + return ret; + } + } + + if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) { + ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement); + if (ret) { + dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable"); + return ret; + } + } + + if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) { + ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement); + if (ret) { + dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable"); + return ret; + } + } + + return ret; +} -- 2.28.0 _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx