Reviewed-by: Luben Tuikov <luben.tuikov@xxxxxxx>
On 2020-08-07 04:48, Liu ChengZhe wrote:
> Some registers are not accessible to virtual function setup, so
> skip their initialization when in VF-SRIOV mode.
>
> v2: move SRIOV VF check into specify functions;
> modify commit description and comment.
>
> Signed-off-by: Liu ChengZhe <ChengZhe.Liu@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 19 +++++++++++++++++++
> drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 19 +++++++++++++++++++
> 2 files changed, 38 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
> index 1f6112b7fa49..80c906a0383f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
> @@ -182,6 +182,12 @@ static void gfxhub_v2_1_init_cache_regs(struct amdgpu_device *adev)
> {
> uint32_t tmp;
>
> + /* These registers are not accessible to VF-SRIOV.
> + * The PF will program them instead.
> + */
> + if (amdgpu_sriov_vf(adev))
> + return;
> +
> /* Setup L2 cache */
> tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);
> tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
> @@ -237,6 +243,12 @@ static void gfxhub_v2_1_enable_system_domain(struct amdgpu_device *adev)
>
> static void gfxhub_v2_1_disable_identity_aperture(struct amdgpu_device *adev)
> {
> + /* These registers are not accessible to VF-SRIOV.
> + * The PF will program them instead.
> + */
> + if (amdgpu_sriov_vf(adev))
> + return;
> +
> WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
> 0xFFFFFFFF);
> WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
> @@ -373,6 +385,13 @@ void gfxhub_v2_1_set_fault_enable_default(struct amdgpu_device *adev,
> bool value)
> {
> u32 tmp;
> +
> + /* These registers are not accessible to VF-SRIOV.
> + * The PF will program them instead.
> + */
> + if (amdgpu_sriov_vf(adev))
> + return;
> +
> tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
> tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
> RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> index d83912901f73..8acb3b625afe 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> @@ -181,6 +181,12 @@ static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
> {
> uint32_t tmp;
>
> + /* These registers are not accessible to VF-SRIOV.
> + * The PF will program them instead.
> + */
> + if (amdgpu_sriov_vf(adev))
> + return;
> +
> /* Setup L2 cache */
> tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
> tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
> @@ -236,6 +242,12 @@ static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev)
>
> static void mmhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev)
> {
> + /* These registers are not accessible to VF-SRIOV.
> + * The PF will program them instead.
> + */
> + if (amdgpu_sriov_vf(adev))
> + return;
> +
> WREG32_SOC15(MMHUB, 0,
> mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
> 0xFFFFFFFF);
> @@ -365,6 +377,13 @@ void mmhub_v2_0_gart_disable(struct amdgpu_device *adev)
> void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
> {
> u32 tmp;
> +
> + /* These registers are not accessible to VF-SRIOV.
> + * The PF will program them instead.
> + */
> + if (amdgpu_sriov_vf(adev))
> + return;
> +
> tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
> tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
> RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
>
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