[AMD Official Use Only - Internal Distribution Only] Reviewed-by: Tao Zhou <tao.zhou1@xxxxxxx> > -----Original Message----- > From: Jiansong Chen <Jiansong.Chen@xxxxxxx> > Sent: Wednesday, July 29, 2020 12:02 PM > To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx > Cc: Zhou1, Tao <Tao.Zhou1@xxxxxxx>; Chen, Jiansong (Simon) > <Jiansong.Chen@xxxxxxx> > Subject: [PATCH] drm/amdgpu: update GC golden setting for navy_flounder > > Update GC golden setting for navy_flounder. > > Signed-off-by: Jiansong Chen <Jiansong.Chen@xxxxxxx> > Change-Id: Ia7e82616b0be48f397c73b015823ac10ef907f08 > --- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > index db9f1e89a0f8..ca16f01956d3 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > @@ -3127,7 +3127,7 @@ static const struct soc15_reg_golden > golden_settings_gc_10_3_2[] = > SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, > 0xff7f0fff, 0x30000100), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, > 0xff7f0fff, 0x7e000100), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, > 0x0000c000), > -SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, > 0x00000200), > +SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, > 0x00000280), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, > 0x00800000), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, > 0x7fff0f1f, 0x00b80000), > SOC15_REG_GOLDEN_VALUE(GC, 0, > mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), @@ -3158,7 > +3158,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_2[] > = > SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, > 0xf0f001ff, 0x00000000), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, > 0xf0f001ff, 0x00000000), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, > 0xf0f001ff, 0x00000000), > -SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xffffffff, > 0x010b0000), > +SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, > 0x01030000), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, > 0x00a00000), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, > 0x00000fff, 0x000003ff) }; > -- > 2.17.1 _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx
