RE: [PATCH 2/2] drm/amdgpu: reconfigure spm golden settings on Navi1x after GFXOFF exit

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[AMD Official Use Only - Internal Distribution Only]

Thanks Feifei!

Rico

-----Original Message-----
From: Xu, Feifei <Feifei.Xu@xxxxxxx>
Sent: Tuesday, July 28, 2020 2:21 PM
To: Yin, Tianci (Rico) <Tianci.Yin@xxxxxxx>; amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Tuikov, Luben <Luben.Tuikov@xxxxxxx>; Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Zhang, Hawking <Hawking.Zhang@xxxxxxx>; Hesik, Christopher <Christopher.Hesik@xxxxxxx>; Swamy, Manjunatha <Manjunatha.Swamy@xxxxxxx>; Quan, Evan <Evan.Quan@xxxxxxx>; Feng, Kenneth <Kenneth.Feng@xxxxxxx>; Yin, Tianci (Rico) <Tianci.Yin@xxxxxxx>
Subject: RE: [PATCH 2/2] drm/amdgpu: reconfigure spm golden settings on Navi1x after GFXOFF exit

[AMD Official Use Only - Internal Distribution Only]

Series is Reviewed-by: Feifei Xu <Feifei Xu@xxxxxxx>

-----Original Message-----
From: Tianci Yin <tianci.yin@xxxxxxx>
Sent: Tuesday, July 28, 2020 1:27 PM
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Tuikov, Luben <Luben.Tuikov@xxxxxxx>; Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Zhang, Hawking <Hawking.Zhang@xxxxxxx>; Xu, Feifei <Feifei.Xu@xxxxxxx>; Hesik, Christopher <Christopher.Hesik@xxxxxxx>; Swamy, Manjunatha <Manjunatha.Swamy@xxxxxxx>; Quan, Evan <Evan.Quan@xxxxxxx>; Feng, Kenneth <Kenneth.Feng@xxxxxxx>; Yin, Tianci (Rico) <Tianci.Yin@xxxxxxx>
Subject: [PATCH 2/2] drm/amdgpu: reconfigure spm golden settings on Navi1x after GFXOFF exit

From: "Tianci.Yin" <tianci.yin@xxxxxxx>

On Navi1x, the SPM golden settings will be lost after GFXOFF enter/exit, reconfigure the golden settings after GFXOFF exit.

Change-Id: I9358ba9c65f241c36f8a35916170b19535148ee9
Signed-off-by: Tianci.Yin <tianci.yin@xxxxxxx>
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 55463e7a11e2..5da0436d41e0 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1309,6 +1309,7 @@ static int smu_enable_umd_pstate(void *handle,

 struct smu_context *smu = (struct smu_context*)(handle);  struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
+struct amdgpu_device *adev = smu->adev;

 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)  return -EINVAL; @@ -1324,6 +1325,16 @@ static int smu_enable_umd_pstate(void *handle,  amdgpu_device_ip_set_clockgating_state(smu->adev,
        AMD_IP_BLOCK_TYPE_GFX,
        AMD_CG_STATE_UNGATE);
+
+if (adev->asic_type >= CHIP_NAVI10 &&
+    adev->asic_type <= CHIP_NAVI12 &&
+    (adev->pm.pp_feature & PP_GFXOFF_MASK)) { if
+(adev->gfx.funcs->init_spm_golden) { dev_dbg(adev->dev,"GFXOFF exited,
+re-init SPM golden settings\n"); amdgpu_gfx_init_spm_golden(adev); }
+else dev_warn(adev->dev,"Callback init_spm_golden is NULL\n"); }
 }
 } else {
 /* exit umd pstate, restore level, enable gfx cg*/
--
2.17.1


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