On Fri, Jul 10, 2020 at 12:48 AM Evan Quan <evan.quan@xxxxxxx> wrote: > > Maximum the code sharing around smu V11. > > Change-Id: Ice0a874f3f70457f1012ca566f9f784ff3e9cd94 > Signed-off-by: Evan Quan <evan.quan@xxxxxxx> Reviewed-by: Alex Deucher <alexander.deucher@xxxxxxx> > --- > drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 4 ++ > drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 38 +++++++++++++++++++ > 2 files changed, 42 insertions(+) > > diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h > index 289c571d6e4e..14d6eef8cf17 100644 > --- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h > +++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h > @@ -285,6 +285,10 @@ int smu_v11_0_get_dpm_level_count(struct smu_context *smu, > enum smu_clk_type clk_type, > uint32_t *value); > > +int smu_v11_0_set_single_dpm_table(struct smu_context *smu, > + enum smu_clk_type clk_type, > + struct smu_11_0_dpm_table *single_dpm_table); > + > int smu_v11_0_get_dpm_level_range(struct smu_context *smu, > enum smu_clk_type clk_type, > uint32_t *min_value, > diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c > index 03be59492af1..7206b9f76042 100644 > --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c > +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c > @@ -1951,6 +1951,44 @@ int smu_v11_0_get_dpm_level_count(struct smu_context *smu, > value); > } > > +int smu_v11_0_set_single_dpm_table(struct smu_context *smu, > + enum smu_clk_type clk_type, > + struct smu_11_0_dpm_table *single_dpm_table) > +{ > + int ret = 0; > + uint32_t clk; > + int i; > + > + ret = smu_v11_0_get_dpm_level_count(smu, > + clk_type, > + &single_dpm_table->count); > + if (ret) { > + dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__); > + return ret; > + } > + > + for (i = 0; i < single_dpm_table->count; i++) { > + ret = smu_v11_0_get_dpm_freq_by_index(smu, > + clk_type, > + i, > + &clk); > + if (ret) { > + dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__); > + return ret; > + } > + > + single_dpm_table->dpm_levels[i].value = clk; > + single_dpm_table->dpm_levels[i].enabled = true; > + > + if (i == 0) > + single_dpm_table->min = clk; > + else if (i == single_dpm_table->count - 1) > + single_dpm_table->max = clk; > + } > + > + return 0; > +} > + > int smu_v11_0_get_dpm_level_range(struct smu_context *smu, > enum smu_clk_type clk_type, > uint32_t *min_value, > -- > 2.27.0 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx