[AMD Public Use]
Hi @Sheng, Wenhui,
I'm thinking of hiding the MP0/MP1 mode 1 reset under AMD_RESET_METHOD_MODE1. the callback function reset is per ASIC function, where nv_asic_reset and soc15_aisc_reset serve for NV series and pre-NV series respectively.
The new mode 1 reset will be used starting from sienna_cichlid. It should be quite strait forward for us to either initialize a flag like is_smu_support_mode1 during sw_init or even check the asic_type in nv_asic_mode1_reset to decide whether we use psp_gpu_reset or smu_gpu_reset.etc.
That's saying, we don't need to change the reset_method interface, where we decide whether we go to BACO/mode reset/pci config space reset.etc. We just differentiate the approach (i.e. psp or smu) in nv_asic_mode1_reset.
Thoughts?
Regards,
Hawking
-----Original Message-----
From: Sheng, Wenhui <Wenhui.Sheng@xxxxxxx>
Sent: Friday, July 10, 2020 13:46
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Zhang, Hawking <Hawking.Zhang@xxxxxxx>; Sheng, Wenhui <Wenhui.Sheng@xxxxxxx>; Gao, Likun <Likun.Gao@xxxxxxx>
Subject: [PATCH 2/4] drm/amdgpu: add psp mode1 reset mode
AMD_RESET_METHOD_MODE1 will be used by SMU
mode1 reset for sienna cichlid, so add
AMD_RESET_METHOD_PSP_MODE1 for psp mode1 reset.
Signed-off-by: Likun Gao <Likun.Gao@xxxxxxx>
Signed-off-by: Wenhui Sheng <Wenhui.Sheng@xxxxxxx>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/nv.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/soc15.c | 6 +++---
4 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 4de93cef79b9..0682a270c17b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -580,7 +580,8 @@ enum amd_reset_method {
AMD_RESET_METHOD_MODE0,
AMD_RESET_METHOD_MODE1,
AMD_RESET_METHOD_MODE2,
- AMD_RESET_METHOD_BACO
+ AMD_RESET_METHOD_BACO,
+ AMD_RESET_METHOD_PSP_MODE1,
};
/*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index fec6cf3f0c8a..565dc59a9e89 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2119,7 +2119,7 @@ static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
*/
switch (amdgpu_asic_reset_method(adev)) {
case AMD_RESET_METHOD_BACO:
- case AMD_RESET_METHOD_MODE1:
+ case AMD_RESET_METHOD_PSP_MODE1:
return true;
default:
return false;
@@ -4174,7 +4174,7 @@ static bool amdgpu_device_lock_adev(struct amdgpu_device *adev, bool trylock)
atomic_inc(&adev->gpu_reset_counter);
adev->in_gpu_reset = true;
switch (amdgpu_asic_reset_method(adev)) {
- case AMD_RESET_METHOD_MODE1:
+ case AMD_RESET_METHOD_PSP_MODE1:
adev->mp1_state = PP_MP1_STATE_SHUTDOWN;
break;
case AMD_RESET_METHOD_MODE2:
@@ -4220,7 +4220,7 @@ static int amdgpu_device_suspend_display_audio(struct amdgpu_device *adev)
*/
reset_method = amdgpu_asic_reset_method(adev);
if ((reset_method != AMD_RESET_METHOD_BACO) &&
- (reset_method != AMD_RESET_METHOD_MODE1))
+ (reset_method != AMD_RESET_METHOD_PSP_MODE1))
return -EINVAL;
p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 356849136d1d..1d27dd3676ad 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -265,7 +265,7 @@ static int nv_asic_mode1_reset(struct amdgpu_device *adev)
amdgpu_atombios_scratch_regs_engine_hung(adev, true);
- dev_info(adev->dev, "GPU mode1 reset\n");
+ dev_info(adev->dev, "GPU psp mode1 reset\n");
/* disable BM */
pci_clear_master(adev->pdev);
@@ -274,7 +274,7 @@ static int nv_asic_mode1_reset(struct amdgpu_device *adev)
ret = psp_gpu_reset(adev);
if (ret)
- dev_err(adev->dev, "GPU mode1 reset failed\n");
+ dev_err(adev->dev, "GPU psp mode1 reset failed\n");
pci_restore_state(adev->pdev);
@@ -310,7 +310,7 @@ nv_asic_reset_method(struct amdgpu_device *adev)
if (!amdgpu_sriov_vf(adev) && smu_baco_is_support(smu))
return AMD_RESET_METHOD_BACO;
else
- return AMD_RESET_METHOD_MODE1;
+ return AMD_RESET_METHOD_PSP_MODE1;
}
static int nv_asic_reset(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 8c739b285915..86ce2f165038 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -479,7 +479,7 @@ static int soc15_asic_mode1_reset(struct amdgpu_device *adev)
amdgpu_atombios_scratch_regs_engine_hung(adev, true);
- dev_info(adev->dev, "GPU mode1 reset\n");
+ dev_info(adev->dev, "GPU psp mode1 reset\n");
/* disable BM */
pci_clear_master(adev->pdev);
@@ -488,7 +488,7 @@ static int soc15_asic_mode1_reset(struct amdgpu_device *adev)
ret = psp_gpu_reset(adev);
if (ret)
- dev_err(adev->dev, "GPU mode1 reset failed\n");
+ dev_err(adev->dev, "GPU psp mode1 reset failed\n");
pci_restore_state(adev->pdev);
@@ -559,7 +559,7 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
if (baco_reset)
return AMD_RESET_METHOD_BACO;
else
- return AMD_RESET_METHOD_MODE1;
+ return AMD_RESET_METHOD_PSP_MODE1;
}
static int soc15_asic_reset(struct amdgpu_device *adev)
--
2.17.1
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