On Thu, Jun 11, 2020 at 7:58 AM Tom St Denis <tom.stdenis@xxxxxxx> wrote: > > Even though they are technically MMIO registers I put the bits with the sqind block > for organizational purposes. > > Requested for UMR debugging. > > Signed-off-by: Tom St Denis <tom.stdenis@xxxxxxx> Reviewed-by: Alex Deucher <alexander.deucher@xxxxxxx> > --- > .../include/asic_reg/gc/gc_10_1_0_offset.h | 3 ++- > .../include/asic_reg/gc/gc_10_1_0_sh_mask.h | 16 ++++++++++++++ > .../include/asic_reg/gc/gc_10_3_0_offset.h | 3 ++- > .../include/asic_reg/gc/gc_10_3_0_sh_mask.h | 16 ++++++++++++++ > .../amd/include/asic_reg/gc/gc_9_0_offset.h | 4 +++- > .../amd/include/asic_reg/gc/gc_9_0_sh_mask.h | 22 +++++++++++++++++++ > .../amd/include/asic_reg/gc/gc_9_1_offset.h | 4 +++- > .../amd/include/asic_reg/gc/gc_9_1_sh_mask.h | 21 ++++++++++++++++++ > .../amd/include/asic_reg/gc/gc_9_2_1_offset.h | 4 +++- > .../include/asic_reg/gc/gc_9_2_1_sh_mask.h | 21 ++++++++++++++++++ > 10 files changed, 109 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h > index 791dc2b3d74a..aab3d22c3b0f 100644 > --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h > +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h > @@ -21,7 +21,8 @@ > #ifndef _gc_10_1_0_OFFSET_HEADER > #define _gc_10_1_0_OFFSET_HEADER > > - > +#define mmSQ_DEBUG_STS_GLOBAL 0x2309 > +#define mmSQ_DEBUG_STS_GLOBAL2 0x2310 > > // addressBlock: gc_sdma0_sdma0dec > // base address: 0x4980 > diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h > index 355e61bed291..4127896ffcdf 100644 > --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h > +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h > @@ -42546,6 +42546,22 @@ > > > // addressBlock: sqind > +//SQ_DEBUG_STS_GLOBAL > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0x000000ffL > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x00000000 > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0x0000ff00L > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x00000008 > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_COMPUTE_MASK 0xff0000L > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_COMPUTE__SHIFT 0x00000010 > +#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x00000001L > +#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x00000000 > +#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x00000002L > +#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x00000001 > +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA0_MASK 0x0000fff0L > +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA0__SHIFT 0x00000004 > +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA1_MASK 0x0fff0000L > +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA1__SHIFT 0x00000010 > + > //SQ_DEBUG_STS_LOCAL > #define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L > #define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x00000000 > diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h > index a9a66371b75e..16c7f6f2467e 100644 > --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h > +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h > @@ -22,7 +22,8 @@ > #ifndef _gc_10_3_0_OFFSET_HEADER > #define _gc_10_3_0_OFFSET_HEADER > > - > +#define mmSQ_DEBUG_STS_GLOBAL 0x2309 > +#define mmSQ_DEBUG_STS_GLOBAL2 0x2310 > > // addressBlock: gc_sdma0_sdma0dec > // base address: 0x4980 > diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h > index 499a8c3c2693..aac57f714cf1 100644 > --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h > +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h > @@ -46269,6 +46269,22 @@ > > > // addressBlock: sqind > +//SQ_DEBUG_STS_GLOBAL > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0x000000ffL > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x00000000 > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0x0000ff00L > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x00000008 > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_COMPUTE_MASK 0xff0000L > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_COMPUTE__SHIFT 0x00000010 > +#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x00000001L > +#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x00000000 > +#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x00000002L > +#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x00000001 > +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA0_MASK 0x0000fff0L > +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA0__SHIFT 0x00000004 > +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA1_MASK 0x0fff0000L > +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA1__SHIFT 0x00000010 > + > //SQ_DEBUG_STS_LOCAL > #define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L > #define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x00000000 > diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h > index fc39795acfda..e3e1a9c1153b 100644 > --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h > +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h > @@ -21,7 +21,9 @@ > #ifndef _gc_9_0_OFFSET_HEADER > #define _gc_9_0_OFFSET_HEADER > > - > +#define mmSQ_DEBUG_STS_GLOBAL 0x2309 > +#define mmSQ_DEBUG_STS_GLOBAL2 0x2310 > +#define mmSQ_DEBUG_STS_GLOBAL3 0x2311 > > // addressBlock: gc_grbmdec > // base address: 0x8000 > diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h > index d7964c2bd950..efc16ddf274a 100644 > --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h > +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h > @@ -28350,6 +28350,28 @@ > > > // addressBlock: sqind > +//SQ_DEBUG_STS_GLOBAL > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0x000000ffL > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x00000000 > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0x0000ff00L > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x00000008 > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK 0xff000000L > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT 0x00000018 > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK 0x00ff0000L > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT 0x00000010 > +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK 0x0000000fL > +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT 0x00000000 > +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK 0x000000f0L > +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT 0x00000004 > +#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x00000001L > +#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x00000000 > +#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x00000002L > +#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x00000001 > +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0x0000fff0L > +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x00000004 > +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0x0fff0000L > +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x00000010 > + > //SQ_DEBUG_STS_LOCAL > #define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L > #define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x00000000 > diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h > index 2223d4b77dcb..6b1ad9082a2c 100644 > --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h > +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h > @@ -21,7 +21,9 @@ > #ifndef _gc_9_1_OFFSET_HEADER > #define _gc_9_1_OFFSET_HEADER > > - > +#define mmSQ_DEBUG_STS_GLOBAL 0x2309 > +#define mmSQ_DEBUG_STS_GLOBAL2 0x2310 > +#define mmSQ_DEBUG_STS_GLOBAL3 0x2311 > > // addressBlock: gc_grbmdec > // base address: 0x8000 > diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h > index 4acf640b1893..b84bd0fa3015 100644 > --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h > +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h > @@ -29571,6 +29571,27 @@ > > > // addressBlock: sqind > +//SQ_DEBUG_STS_GLOBAL > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0x000000ffL > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x00000000 > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0x0000ff00L > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x00000008 > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK 0xff000000L > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT 0x00000018 > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK 0x00ff0000L > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT 0x00000010 > +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK 0x0000000fL > +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT 0x00000000 > +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK 0x000000f0L > +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT 0x00000004 > +#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x00000001L > +#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x00000000 > +#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x00000002L > +#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x00000001 > +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0x0000fff0L > +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x00000004 > +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0x0fff0000L > +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x00000010 > //SQ_DEBUG_STS_LOCAL > #define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L > #define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x00000000 > diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h > index 1c5ef8e8a341..f377354e850e 100644 > --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h > +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h > @@ -21,7 +21,9 @@ > #ifndef _gc_9_2_1_OFFSET_HEADER > #define _gc_9_2_1_OFFSET_HEADER > > - > +#define mmSQ_DEBUG_STS_GLOBAL 0x2309 > +#define mmSQ_DEBUG_STS_GLOBAL2 0x2310 > +#define mmSQ_DEBUG_STS_GLOBAL3 0x2311 > > // addressBlock: gc_grbmdec > // base address: 0x8000 > diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h > index 088f59cc2197..6199fce51e20 100644 > --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h > +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h > @@ -29893,6 +29893,27 @@ > > > // addressBlock: sqind > +//SQ_DEBUG_STS_GLOBAL > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0x000000ffL > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x00000000 > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0x0000ff00L > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x00000008 > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK 0xff000000L > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT 0x00000018 > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK 0x00ff0000L > +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT 0x00000010 > +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK 0x0000000fL > +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT 0x00000000 > +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK 0x000000f0L > +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT 0x00000004 > +#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x00000001L > +#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x00000000 > +#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x00000002L > +#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x00000001 > +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0x0000fff0L > +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x00000004 > +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0x0fff0000L > +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x00000010 > //SQ_DEBUG_STS_LOCAL > #define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L > #define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x00000000 > -- > 2.26.2 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx