[AMD Official Use Only - Internal Distribution Only]
According to reg_offset assignment in amdgpu_discovery_reg_base_init() the reg_offset is calculated as IP base address pointer therefore PWR IP base should be map to adev->reg_offset[SMUIO_HWIP][0] + 1. Moreover, not sure whether can use/need the mapped address to access PWR_MISC_CNTL_STATUS for controlling the GFX CGPG in Renoir.
Base on the above modify the PWR IP access nullptr issue should can be fix, but should hold on this patch since start X will be occur other nullptr issue during amdgpu_info_ioctl().
Thanks,
Prike
> -----Original Message-----
> From: Alex Deucher <alexdeucher@xxxxxxxxx>
> Sent: Friday, June 5, 2020 11:40 PM
> To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx; Liang, Prike <Prike.Liang@xxxxxxx>
> Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx>
> Subject: [PATCH] drm/amdgpu/soc15: fix using ip discovery tables on renoir
> (v2)
>
> The PWR block moved into SMUIO, so the ip discovery table doesn't have an
> entry for PWR, but the register has the same absolute offset, so just patch up
> the offsets after updating the offsets from the IP discovery table.
>
> v2: PWR became SMUIO block 1. fix the mapping.
>
> Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/soc15.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 623745b2d8b3..dd17a8422111 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -686,6 +686,9 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
> DRM_WARN("failed to init reg base from ip
> discovery table, "
> "fallback to legacy init method\n");
> vega10_reg_base_init(adev);
> +} else {
> +/* PWR block was merged into SMUIO on
> renoir and became SMUIO block 1 */
> +adev->reg_offset[PWR_HWIP][0] = adev-
> >reg_offset[SMUIO_HWIP][1];
> }
> }
> break;
> --
> 2.25.4
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