On Fri, Jun 5, 2020 at 11:34 AM Alex Deucher <alexdeucher@xxxxxxxxx> wrote:
>
> The PWR block moved into SMUIO, so the ip discovery table
> doesn't have an entry for PWR, but the register has the
> same absolute offset, so just patch up the offsets after
> updating the offsets from the IP discovery table.
>
> Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
Nevermind. this won't work.
> ---
> drivers/gpu/drm/amd/amdgpu/soc15.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 623745b2d8b3..21f29685f158 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -670,7 +670,7 @@ static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
>
> int soc15_set_ip_blocks(struct amdgpu_device *adev)
> {
> - int r;
> + int r, i;
>
> /* Set IP register base before any HW register access */
> switch (adev->asic_type) {
> @@ -686,6 +686,10 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
> DRM_WARN("failed to init reg base from ip discovery table, "
> "fallback to legacy init method\n");
> vega10_reg_base_init(adev);
> + } else {
> + /* PWR block was merged into SMUIO on renoir */
> + for (i = 0 ; i < HWIP_MAX_INSTANCE; ++i)
> + adev->reg_offset[PWR_HWIP][i] = adev->reg_offset[SMUIO_HWIP][i];
> }
> }
> break;
> --
> 2.25.4
>
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