Hello Bhawanpreet Lakha,
This is a semi-automatic email about new static checker warnings.
The patch 581b9589487e: "drm/amd/display: Add DCN3 HWSEQ" from May
21, 2020, leads to the following Smatch complaint:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:463 dcn30_init_hw()
warn: variable dereferenced before check 'res_pool->dccg' (see line 437)
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c
436 // Initialize the dccg
437 if (res_pool->dccg->funcs->dccg_init)
^^^^^^^^^^^^^^
The patch adds a dereference.
438 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
439
440 //Enable ability to power gate / don't force power on permanently
441 hws->funcs.enable_power_gating_plane(dc->hwseq, true);
442
443 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
444 REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
445 REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
446
447 hws->funcs.dccg_init(hws);
448
449 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
450 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
451 REG_WRITE(REFCLK_CNTL, 0);
452 } else {
453 if (!dcb->funcs->is_accelerated_mode(dcb)) {
454 hws->funcs.bios_golden_init(dc);
455 hws->funcs.disable_vga(dc->hwseq);
456 }
457
458 if (dc->ctx->dc_bios->fw_info_valid) {
459 res_pool->ref_clocks.xtalin_clock_inKhz =
460 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
461
462 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
463 if (res_pool->dccg && res_pool->hubbub) {
^^^^^^^^^^^^^^
This check is too late.
464
465 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
regards,
dan carpenter
_______________________________________________
amd-gfx mailing list
amd-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
