On Thu, Jun 4, 2020 at 12:46 AM Evan Quan <evan.quan@xxxxxxx> wrote:
>
> By moving ASIC specific code into its own file.
You might want to clarify that the macros check if the asic has the
callback, so no need to explicitly check. With that fixed:
Reviewed-by: Alex Deucher <alexander.deucher@xxxxxxx>
>
> Change-Id: Ib6775c1c8c5211ea45db6c3fb604a8279411ab37
> Signed-off-by: Evan Quan <evan.quan@xxxxxxx>
> ---
> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 59 +++++++------------
> drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 8 +--
> drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 18 ++++++
> .../drm/amd/powerplay/sienna_cichlid_ppt.c | 6 +-
> drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 5 --
> 5 files changed, 45 insertions(+), 51 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 78ab0d46eddd..b2c1ad95edf7 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -1055,12 +1055,9 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
> return 0;
> }
>
> - if (adev->asic_type != CHIP_ARCTURUS &&
> - adev->asic_type != CHIP_SIENNA_CICHLID) {
> - ret = smu_init_display_count(smu, 0);
> - if (ret)
> - return ret;
> - }
> + ret = smu_init_display_count(smu, 0);
> + if (ret)
> + return ret;
>
> if (initialize) {
> /* get boot_values from vbios to set revision, gfxclk, and etc. */
> @@ -1134,21 +1131,10 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
> if (ret)
> return ret;
>
> - if (adev->asic_type == CHIP_NAVI10) {
> - if ((adev->pdev->device == 0x731f && (adev->pdev->revision == 0xc2 ||
> - adev->pdev->revision == 0xc3 ||
> - adev->pdev->revision == 0xca ||
> - adev->pdev->revision == 0xcb)) ||
> - (adev->pdev->device == 0x66af && (adev->pdev->revision == 0xf3 ||
> - adev->pdev->revision == 0xf4 ||
> - adev->pdev->revision == 0xf5 ||
> - adev->pdev->revision == 0xf6))) {
> - ret = smu_disable_umc_cdr_12gbps_workaround(smu);
> - if (ret) {
> - pr_err("Workaround failed to disable UMC CDR feature on 12Gbps SKU!\n");
> - return ret;
> - }
> - }
> + ret = smu_disable_umc_cdr_12gbps_workaround(smu);
> + if (ret) {
> + pr_err("Workaround failed to disable UMC CDR feature on 12Gbps SKU!\n");
> + return ret;
> }
>
> if (smu->ppt_funcs->set_power_source) {
> @@ -1166,20 +1152,17 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
> }
> }
>
> - if (adev->asic_type != CHIP_ARCTURUS &&
> - adev->asic_type != CHIP_SIENNA_CICHLID) {
> - ret = smu_notify_display_change(smu);
> - if (ret)
> - return ret;
> + ret = smu_notify_display_change(smu);
> + if (ret)
> + return ret;
>
> - /*
> - * Set min deep sleep dce fclk with bootup value from vbios via
> - * SetMinDeepSleepDcefclk MSG.
> - */
> - ret = smu_set_min_dcef_deep_sleep(smu);
> - if (ret)
> - return ret;
> - }
> + /*
> + * Set min deep sleep dce fclk with bootup value from vbios via
> + * SetMinDeepSleepDcefclk MSG.
> + */
> + ret = smu_set_min_dcef_deep_sleep(smu);
> + if (ret)
> + return ret;
>
> /*
> * Set initialized values (get from vbios) to dpm tables context such as
> @@ -1196,11 +1179,9 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
> return ret;
> }
>
> - if (adev->asic_type != CHIP_ARCTURUS) {
> - ret = smu_override_pcie_parameters(smu);
> - if (ret)
> - return ret;
> - }
> + ret = smu_override_pcie_parameters(smu);
> + if (ret)
> + return ret;
>
> ret = smu_set_default_od_settings(smu, initialize);
> if (ret)
> diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> index df7b408319f7..1de5304d12bf 100644
> --- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> @@ -2463,16 +2463,16 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
> .populate_smc_tables = smu_v11_0_populate_smc_pptable,
> .check_fw_version = smu_v11_0_check_fw_version,
> .write_pptable = smu_v11_0_write_pptable,
> - .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
> + .set_min_dcef_deep_sleep = NULL,
> .set_driver_table_location = smu_v11_0_set_driver_table_location,
> .set_tool_table_location = smu_v11_0_set_tool_table_location,
> .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
> .system_features_control = smu_v11_0_system_features_control,
> .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
> - .init_display_count = smu_v11_0_init_display_count,
> + .init_display_count = NULL,
> .set_allowed_mask = smu_v11_0_set_allowed_mask,
> .get_enabled_mask = smu_v11_0_get_enabled_mask,
> - .notify_display_change = smu_v11_0_notify_display_change,
> + .notify_display_change = NULL,
> .set_power_limit = smu_v11_0_set_power_limit,
> .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
> .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
> @@ -2496,7 +2496,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
> .baco_exit = smu_v11_0_baco_exit,
> .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
> .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
> - .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
> + .override_pcie_parameters = NULL,
> .get_pptable_power_limit = arcturus_get_pptable_power_limit,
> .set_df_cstate = arcturus_set_df_cstate,
> .allow_xgmi_power_down = arcturus_allow_xgmi_power_down,
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> index 68142f6798c6..a43c16befffd 100644
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> @@ -2209,12 +2209,30 @@ static int navi10_dummy_pstate_control(struct smu_context *smu, bool enable)
> return result;
> }
>
> +static inline bool navi10_need_umc_cdr_12gbps_workaround(struct amdgpu_device *adev)
> +{
> + if (adev->asic_type != CHIP_NAVI10)
> + return false;
> +
> + if (adev->pdev->device == 0x731f &&
> + (adev->pdev->revision == 0xc2 ||
> + adev->pdev->revision == 0xc3 ||
> + adev->pdev->revision == 0xca ||
> + adev->pdev->revision == 0xcb))
> + return true;
> + else
> + return false;
> +}
> +
> static int navi10_disable_umc_cdr_12gbps_workaround(struct smu_context *smu)
> {
> uint32_t uclk_count, uclk_min, uclk_max;
> uint32_t smu_version;
> int ret = 0;
>
> + if (!navi10_need_umc_cdr_12gbps_workaround(smu->adev))
> + return 0;
> +
> ret = smu_get_smc_version(smu, NULL, &smu_version);
> if (ret)
> return ret;
> diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
> index ce16cabb0780..f83df6adcbce 100644
> --- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
> @@ -2463,16 +2463,16 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
> .populate_smc_tables = smu_v11_0_populate_smc_pptable,
> .check_fw_version = smu_v11_0_check_fw_version,
> .write_pptable = smu_v11_0_write_pptable,
> - .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
> + .set_min_dcef_deep_sleep = NULL,
> .set_driver_table_location = smu_v11_0_set_driver_table_location,
> .set_tool_table_location = smu_v11_0_set_tool_table_location,
> .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
> .system_features_control = smu_v11_0_system_features_control,
> .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
> - .init_display_count = smu_v11_0_init_display_count,
> + .init_display_count = NULL,
> .set_allowed_mask = smu_v11_0_set_allowed_mask,
> .get_enabled_mask = smu_v11_0_get_enabled_mask,
> - .notify_display_change = smu_v11_0_notify_display_change,
> + .notify_display_change = NULL,
> .set_power_limit = smu_v11_0_set_power_limit,
> .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
> .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
> diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> index 06b376a1396d..d4509ceb7854 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> @@ -836,11 +836,6 @@ int smu_v11_0_set_tool_table_location(struct smu_context *smu)
> int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
> {
> int ret = 0;
> - struct amdgpu_device *adev = smu->adev;
> -
> - /* Sienna_Cichlid do not support to change display num currently */
> - if (adev->asic_type == CHIP_SIENNA_CICHLID)
> - return 0;
>
> if (!smu->pm_enabled)
> return ret;
> --
> 2.27.0
>
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