[AMD Official Use Only - Internal Distribution Only] Reviewed-by: Hawking Zhang <Hawking.Zhang@xxxxxxx> Regards, Hawking -----Original Message----- From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Alex Deucher Sent: Thursday, May 28, 2020 04:29 To: amd-gfx list <amd-gfx@xxxxxxxxxxxxxxxxxxxxx> Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx> Subject: Re: [PATCH] drm/amdgpu/gmc10: program the smallK fragment size Ping? On Fri, May 22, 2020 at 6:17 PM Alex Deucher <alexdeucher@xxxxxxxxx> wrote: > > Explicitly set the smallk size to 0 (4k). This is the hw default, but > set it anyway just in case something else changed it. > > Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx> > --- > drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 4 ++++ > drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 4 ++++ > 2 files changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c > b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c > index cc866c367939..6939edfc5232 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c > @@ -181,6 +181,10 @@ static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev) > tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); > tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); > WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp); > + > + tmp = mmGCVM_L2_CNTL5_DEFAULT; > + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); > + WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp); > } > > static void gfxhub_v2_0_enable_system_domain(struct amdgpu_device > *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c > b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c > index fb3f228458e5..616309e85d6e 100644 > --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c > @@ -164,6 +164,10 @@ static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev) > tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); > tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); > WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL4, tmp); > + > + tmp = mmMMVM_L2_CNTL5_DEFAULT; > + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); > + WREG32_SOC15(GC, 0, mmMMVM_L2_CNTL5, tmp); > } > > static void mmhub_v2_0_enable_system_domain(struct amdgpu_device > *adev) > -- > 2.25.4 > _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Chawking.zhang%40amd.com%7C15145b8fc17c4f7b412d08d8027cb12c%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637262081875240018&sdata=79%2ByW9LaK1bgmZueFC68qhWvJGbSg%2FVf8OnW1B7bwTg%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx
