On Fri, May 22, 2020 at 3:39 PM Gavin Wan <Gavin.Wan@xxxxxxx> wrote: > > For SRIOV, since the CP_INT_CNTL_RING0 is programed on host side. > The Guest should not program CP_INT_CNTL_RING0 again. > > Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1 > Signed-off-by: Gavin Wan <Gavin.Wan@xxxxxxx> Acked-by: Alex Deucher <alexander.deucher@xxxxxxx> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > index bd5dd4f64311..4d6928cfc269 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > @@ -4558,7 +4558,12 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev) > static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, > bool enable) > { > - u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); > + u32 tmp; > + > + if (amdgpu_sriov_vf(adev)) > + return; > + > + tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); > > tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, > enable ? 1 : 0); > -- > 2.25.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx