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[AMD Public Use]
Series is:
Reviewed-by: Alex Deucher <alexander.deucher@xxxxxxx>
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> on behalf of Kent Russell <kent.russell@xxxxxxx>
Sent: Thursday, May 7, 2020 2:54 PM To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx <amd-gfx@xxxxxxxxxxxxxxxxxxxxx> Cc: Russell, Kent <Kent.Russell@xxxxxxx> Subject: [PATCH 2/2] Revert "drm/amdgpu: Add ReadSerial defines for Arcturus" This reverts commit a0d4939d8616fab676699dab8ba3cbe519d4a8e9.
SMU does not support this on Arcturus right now Signed-off-by: Kent Russell <kent.russell@xxxxxxx> Change-Id: I50efa3695570302231986d56c2351aac331726ca --- drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 2 -- drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h | 3 --- 2 files changed, 5 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c index e98d92ec1eac..1c66b7d7139c 100644 --- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c @@ -128,8 +128,6 @@ static struct smu_11_0_cmn2aisc_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] MSG_MAP(SetXgmiMode, PPSMC_MSG_SetXgmiMode), MSG_MAP(SetMemoryChannelEnable, PPSMC_MSG_SetMemoryChannelEnable), MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl), - MSG_MAP(ReadSerialNumTop32, PPSMC_MSG_ReadSerialNumTop32), - MSG_MAP(ReadSerialNumBottom32, PPSMC_MSG_ReadSerialNumBottom32), }; static struct smu_11_0_cmn2aisc_mapping arcturus_clk_map[SMU_CLK_COUNT] = { diff --git a/drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h index b426be7c76c6..f736d773f9d6 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h +++ b/drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h @@ -116,9 +116,6 @@ #define PPSMC_MSG_DFCstateControl 0x3B #define PPSMC_Message_Count 0x3C -#define PPSMC_MSG_ReadSerialNumTop32 0x49 -#define PPSMC_MSG_ReadSerialNumBottom32 0x4A - typedef uint32_t PPSMC_Result; typedef uint32_t PPSMC_Msg; #pragma pack(pop) -- 2.17.1 _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://nam11.safelinks.protection.outlook.com/?url=""> |
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