Ping?
On Tue, May 5, 2020 at 12:42 PM Alex Deucher <alexdeucher@xxxxxxxxx> wrote:
>
> Same as gfx9. This allows us to kill the waves for hung
> shaders.
>
> Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index ddb485e1e963..27c63a8f698c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -7690,6 +7690,19 @@ static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
> ref, mask);
> }
>
> +static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
> + unsigned vmid)
> +{
> + struct amdgpu_device *adev = ring->adev;
> + uint32_t value = 0;
> +
> + value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
> + value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
> + value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
> + value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
> + WREG32_SOC15(GC, 0, mmSQ_CMD, value);
> +}
> +
> static void
> gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
> uint32_t me, uint32_t pipe,
> @@ -8105,6 +8118,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
> .emit_wreg = gfx_v10_0_ring_emit_wreg,
> .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
> .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
> + .soft_recovery = gfx_v10_0_ring_soft_recovery,
> .emit_mem_sync = gfx_v10_0_emit_mem_sync,
> };
>
> --
> 2.25.4
>
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