Re: drm/amdgpu: invalidate L2 before SDMA IBs (on gfx10)

[Marek Olšák <maraeo@xxxxxxxxx>]

I'll answer two questions asked:

1) SDMA doesn't need GCR at the end of IBs. It's because SDMA writes bypass GL2 and at the same time they invalidate all cache lines they touch.

2)

> If we always insert a GL2C invalidate at every EOP of every IB from every engine, why we need a GL2C invalidate before IB  execute ?

I just sent you a counterexample on a private thread that proves that invalidation in RELEASE_MEM doesn't accomplish anything. The invalidation flag is there because:

1) it was inherited from gfx9, which was inherited from gfx8, which was inherited from gfx7, which doesn't have the WB flag, so INV has to be used instead.

2) to hide bugs

Marek

On Wed, Apr 29, 2020 at 7:24 AM Liu, Monk <Monk.Liu@xxxxxxx> wrote:

>> Well from my understanding I think that a G2LC invalidation is still necessary before an IB executes.

Agree, I think before an IB executes the only thing we need on GL2C is the invalidation, not the flush .

>> The problem is that the memory of the IB could also be cached because of some activity of the GFX or Compute rings.

If we always insert a GL2C invalidate at every EOP of every IB from every engine, why we need a GL2C invalidate before IB  execute ?

_____________________________________

Monk Liu|GPU Virtualization Team |AMD

 

From: Koenig, Christian <Christian.Koenig@xxxxxxx>
Sent: Wednesday, April 29, 2020 5:38 PM
To: Liu, Monk <Monk.Liu@xxxxxxx>; Marek Olšák <maraeo@xxxxxxxxx>; amd-gfx mailing list <amd-gfx@xxxxxxxxxxxxxxxxxxxxx>
Subject: Re: drm/amdgpu: invalidate L2 before SDMA IBs (on gfx10)

 

Well from my understanding I think that a G2LC invalidation is still necessary before an IB executes.

The problem is that the memory of the IB could also be cached because of some activity of the GFX or Compute rings.

Regards,
Christian.

Am 29.04.20 um 11:35 schrieb Liu, Monk:

Here is the reason we should always insert a “sync mem” packet at the FENCE place of SDMA, not before IB emit.

 

By always inserting “sync mem” in the FENCE place we can make sure:1

1. data is really flushed to system memory before CPU try to read it
2. all the G2LC is invalidated by “sync mem”, thus in the next round SDMA IB, it won’t get staled data from G2LC cache

 

by inserting “sync mem” in prior to IB could only achieve :  Avoid get staled data in g2lc during IB execution

 

for GFX/COMPUTE ring since they have release_mem packet so it is inherently doing the G2LC flush and invalidate upon a fence signaled

 

_____________________________________

Monk Liu|GPU Virtualization Team |AMD

 

From: Liu, Monk
Sent: Wednesday, April 29, 2020 5:06 PM
To: 'Marek Olšák' <maraeo@xxxxxxxxx>; amd-gfx mailing list <amd-gfx@xxxxxxxxxxxxxxxxxxxxx>; Koenig, Christian <Christian.Koenig@xxxxxxx>
Subject: RE: drm/amdgpu: invalidate L2 before SDMA IBs (on gfx10)

 

Hi @Koenig, Christian & Marek

 

I still have some concerns regarding Marek’s patch, correct me if I’m wrong

 

See that Marek put a SDMA_OP_GCR_REQ before emitting IB, to make sure SDMA won’t get stale cache data during the IB execution.

 

But that “SDMA_OP_GCR_REQ” only invalidate/flush the GFXHUB’s G2LC cache right ?  what if the memory is changed by MM or CPU (out side of GFXHUB) ?

 

Can this “ SDMA_OP_GCR_REQ” force MMHUB or even CPU to flush their operation result from their cache to memory ??

 

Besides, with my understanding the “EOP” of gfx ring is doing the thing of “invalidate/flush” L2 cache upon a fence signaled, so what we should do on SDMA5 is to insert this “SDMA_OP_GCR_REQ”

Right before thee “emit_fence” of SDMA  (this is what windows KMD do)

 

thanks

_____________________________________

Monk Liu|GPU Virtualization Team |AMD

 

From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Marek Ol?ák
Sent: Saturday, April 25, 2020 4:52 PM
To: amd-gfx mailing list <amd-gfx@xxxxxxxxxxxxxxxxxxxxx>
Subject: drm/amdgpu: invalidate L2 before SDMA IBs (on gfx10)

 

This should fix SDMA hangs on gfx10.

 

Marek

 

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