[AMD Official Use Only - Internal Distribution Only]
Sorry I shall say hold on this patch until we reach agreement on how to support onevf mode in current software smu design.
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Zhang, Hawking
Sent: Monday, April 27, 2020 12:25
To: Liu, Monk <Monk.Liu@xxxxxxx>; amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Liu, Monk <Monk.Liu@xxxxxxx>
Subject: RE: [PATCH] drm/amdgpu: fix one vf mode
[AMD Official Use Only - Internal Distribution Only]
As discussed, we want to keep this patch until we finalized onevf mode support design in guest driver.
Current approach to add one_vf mode check for every smu function is not sustatinable and error prone when new asic support added in software smu
Regards,
Hawking
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Monk Liu
Sent: Monday, April 27, 2020 11:35
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Liu, Monk <Monk.Liu@xxxxxxx>
Subject: [PATCH] drm/amdgpu: fix one vf mode
still need to call system_enable_features for one vf mode but need to block the SMU request from SRIOV case and allows the software side change pass in "smu_v11_0_system_features_control"
by this patlch the pp_dpm_mclk/sclk now shows correct output
Signed-off-by: Monk Liu <Monk.Liu@xxxxxxx>
Singed-off-by: Rohit <rohit.khaire@xxxxxxx>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 8 ++++++++ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 13 +++++++++----
2 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 5964d63..bfb026c 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1183,7 +1183,15 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
return ret;
}
}
+ } else {
+ /* we need to enable some SMU features for one vf mode */
+ if (amdgpu_sriov_is_pp_one_vf(adev)) {
+ ret = smu_system_features_control(smu, true);
+ if (ret)
+ return ret;
+ }
}
+
if (adev->asic_type != CHIP_ARCTURUS) {
ret = smu_notify_display_change(smu);
if (ret)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 3e1b3ed..6fb2fd1 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -764,6 +764,9 @@ int smu_v11_0_write_pptable(struct smu_context *smu)
struct smu_table_context *table_context = &smu->smu_table;
int ret = 0;
+ if (amdgpu_sriov_vf(smu->adev))
+ return 0;
+
ret = smu_update_table(smu, SMU_TABLE_PPTABLE, 0,
table_context->driver_pptable, true);
@@ -922,10 +925,12 @@ int smu_v11_0_system_features_control(struct smu_context *smu,
uint32_t feature_mask[2];
int ret = 0;
- ret = smu_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
- SMU_MSG_DisableAllSmuFeatures), NULL);
- if (ret)
- return ret;
+ if (!amdgpu_sriov_vf(smu->adev)) {
+ ret = smu_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
+ SMU_MSG_DisableAllSmuFeatures), NULL);
+ if (ret)
+ return ret;
+ }
bitmap_zero(feature->enabled, feature->feature_num);
bitmap_zero(feature->supported, feature->feature_num);
--
2.7.4
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