Am 2020-04-17 um 6:54 p.m. schrieb Joseph Greathouse:
> In order to surface the ASIC revision to user level, we want
> to put it into the HSA topology. This can be because different
> ASIC revisions may require user-level software to do different
> things (e.g. patch code for things that are changed in later
> hardware revisions).
>
> The ASIC revision from the hardware is maximum of 4 bits at this
> time, so put it into 4 of the open bits in the HSA capability.
> Then user-level software can use this capability information to
> know -- for each ASIC -- what revision-based things must be done.
>
> Signed-off-by: Joseph Greathouse <Joseph.Greathouse@xxxxxxx>
Reviewed-by: Felix Kuehling <Felix.Kuehling@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 7 +++++++
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 1 +
> drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 4 ++++
> drivers/gpu/drm/amd/amdkfd/kfd_topology.h | 5 ++++-
> 4 files changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> index abfbe89e805e..ad59ac4423b8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> @@ -564,6 +564,13 @@ uint32_t amdgpu_amdkfd_get_num_gws(struct kgd_dev *kgd)
> return adev->gds.gws_size;
> }
>
> +uint32_t amdgpu_amdkfd_get_asic_rev_id(struct kgd_dev *kgd)
> +{
> + struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
> +
> + return adev->rev_id;
> +}
> +
> int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
> uint32_t vmid, uint64_t gpu_addr,
> uint32_t *ib_cmd, uint32_t ib_len)
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> index 13feb313e9b3..d065c50582eb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> @@ -175,6 +175,7 @@ uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd);
> uint64_t amdgpu_amdkfd_get_unique_id(struct kgd_dev *kgd);
> uint64_t amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev *kgd);
> uint32_t amdgpu_amdkfd_get_num_gws(struct kgd_dev *kgd);
> +uint32_t amdgpu_amdkfd_get_asic_rev_id(struct kgd_dev *kgd);
> uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *src);
>
> /* Read user wptr from a specified user address space with page fault
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> index 5db42814dd51..6e52c95ce8b0 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> @@ -1303,6 +1303,10 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
>
> dev->node_props.vendor_id = gpu->pdev->vendor;
> dev->node_props.device_id = gpu->pdev->device;
> + dev->node_props.capability |=
> + ((amdgpu_amdkfd_get_asic_rev_id(dev->gpu->kgd) <<
> + HSA_CAP_ASIC_REVISION_SHIFT) &
> + HSA_CAP_ASIC_REVISION_MASK);
> dev->node_props.location_id = pci_dev_id(gpu->pdev);
> dev->node_props.max_engine_clk_fcompute =
> amdgpu_amdkfd_get_max_engine_clock_in_mhz(dev->gpu->kgd);
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
> index 46eeecaf1b68..0c51bd3dcd59 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
> @@ -41,7 +41,6 @@
> #define HSA_CAP_WATCH_POINTS_TOTALBITS_SHIFT 8
> #define HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK 0x00003000
> #define HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT 12
> -#define HSA_CAP_RESERVED 0xffffc000
>
> #define HSA_CAP_DOORBELL_TYPE_PRE_1_0 0x0
> #define HSA_CAP_DOORBELL_TYPE_1_0 0x1
> @@ -51,6 +50,10 @@
> #define HSA_CAP_SRAM_EDCSUPPORTED 0x00080000
> #define HSA_CAP_MEM_EDCSUPPORTED 0x00100000
> #define HSA_CAP_RASEVENTNOTIFY 0x00200000
> +#define HSA_CAP_ASIC_REVISION_MASK 0x03c00000
> +#define HSA_CAP_ASIC_REVISION_SHIFT 22
> +
> +#define HSA_CAP_RESERVED 0xfc078000
>
> struct kfd_node_properties {
> uint64_t hive_id;
_______________________________________________
amd-gfx mailing list
amd-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
