On Sat, 4 Apr 2020 16:32:24 +0200 Peter Zijlstra <peterz@xxxxxxxxxxxxx> wrote: > On Sat, Apr 04, 2020 at 12:08:08PM +0900, Masami Hiramatsu wrote: > > From c609be0b6403245612503fca1087628655bab96c Mon Sep 17 00:00:00 2001 > > From: Masami Hiramatsu <mhiramat@xxxxxxxxxx> > > Date: Fri, 3 Apr 2020 16:58:22 +0900 > > Subject: [PATCH] x86: insn: Add insn_is_fpu() > > > > Add insn_is_fpu(insn) which tells that the insn is > > whether touch the MMX/XMM/YMM register or the instruction > > of FP coprocessor. > > Looks good, although I changed it a little like so: OK, and I found there is a mistake on my patch. I should not use (v) for the instruction, which makes decoder insane. > > --- a/arch/x86/include/asm/insn.h > +++ b/arch/x86/include/asm/insn.h > @@ -133,11 +133,12 @@ static inline int insn_is_fpu(struct ins > { > if (!insn->opcode.got) > insn_get_opcode(insn); > - if (inat_is_fpu(insn->attr)) { > + if (inat_is_fpu(insn->attr)) { > if (insn->attr & INAT_FPUIFVEX) > return insn_is_avx(insn); > return 1; > } > + return 0; > } > > static inline int insn_has_emulate_prefix(struct insn *insn) > --- a/arch/x86/lib/x86-opcode-map.txt > +++ b/arch/x86/lib/x86-opcode-map.txt > @@ -269,14 +269,14 @@ d4: AAM Ib (i64) > d5: AAD Ib (i64) > d6: > d7: XLAT/XLATB > -d8: ESC > -d9: ESC > -da: ESC > -db: ESC > -dc: ESC > -dd: ESC > -de: ESC > -df: ESC > +d8: FPU > +d9: FPU > +da: FPU > +db: FPU > +dc: FPU > +dd: FPU > +de: FPU > +df: FPU I don't want to use FPU since Intel SDM is still using ESC because it is co-processor escape code. Here is the new patch. >From d7eca4946ab3f0d08ad1268f49418f8655aaf57c Mon Sep 17 00:00:00 2001 From: Masami Hiramatsu <mhiramat@xxxxxxxxxx> Date: Fri, 3 Apr 2020 16:58:22 +0900 Subject: [PATCH] x86: insn: Add insn_is_fpu() Add insn_is_fpu(insn) which tells that the insn is whether touch the MMX/XMM/YMM register or the instruction of FP coprocessor. Signed-off-by: Masami Hiramatsu <mhiramat@xxxxxxxxxx> --- Changes: - Fix SET* also not FPU (unless it has vex prefix.) - Fix to remove (v) (VEX only) flag. --- arch/x86/include/asm/inat.h | 7 +++++++ arch/x86/include/asm/insn.h | 12 ++++++++++++ arch/x86/lib/x86-opcode-map.txt | 6 +++--- arch/x86/tools/gen-insn-attr-x86.awk | 22 +++++++++++++++++----- tools/arch/x86/include/asm/inat.h | 7 +++++++ tools/arch/x86/include/asm/insn.h | 12 ++++++++++++ tools/arch/x86/lib/x86-opcode-map.txt | 6 +++--- tools/arch/x86/tools/gen-insn-attr-x86.awk | 22 +++++++++++++++++----- 8 files changed, 78 insertions(+), 16 deletions(-) diff --git a/arch/x86/include/asm/inat.h b/arch/x86/include/asm/inat.h index 4cf2ad521f65..ffce45178c08 100644 --- a/arch/x86/include/asm/inat.h +++ b/arch/x86/include/asm/inat.h @@ -77,6 +77,8 @@ #define INAT_VEXOK (1 << (INAT_FLAG_OFFS + 5)) #define INAT_VEXONLY (1 << (INAT_FLAG_OFFS + 6)) #define INAT_EVEXONLY (1 << (INAT_FLAG_OFFS + 7)) +#define INAT_FPU (1 << (INAT_FLAG_OFFS + 8)) +#define INAT_FPUIFVEX (1 << (INAT_FLAG_OFFS + 9)) /* Attribute making macros for attribute tables */ #define INAT_MAKE_PREFIX(pfx) (pfx << INAT_PFX_OFFS) #define INAT_MAKE_ESCAPE(esc) (esc << INAT_ESC_OFFS) @@ -227,4 +229,9 @@ static inline int inat_must_evex(insn_attr_t attr) { return attr & INAT_EVEXONLY; } + +static inline int inat_is_fpu(insn_attr_t attr) +{ + return attr & INAT_FPU; +} #endif diff --git a/arch/x86/include/asm/insn.h b/arch/x86/include/asm/insn.h index 5c1ae3eff9d4..1752c54d2103 100644 --- a/arch/x86/include/asm/insn.h +++ b/arch/x86/include/asm/insn.h @@ -129,6 +129,18 @@ static inline int insn_is_evex(struct insn *insn) return (insn->vex_prefix.nbytes == 4); } +static inline int insn_is_fpu(struct insn *insn) +{ + if (!insn->opcode.got) + insn_get_opcode(insn); + if (inat_is_fpu(insn->attr)) { + if (insn->attr & INAT_FPUIFVEX) + return insn_is_avx(insn); + return 1; + } + return 0; +} + static inline int insn_has_emulate_prefix(struct insn *insn) { return !!insn->emulate_prefix_size; diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt index ec31f5b60323..c3d36b4c894d 100644 --- a/arch/x86/lib/x86-opcode-map.txt +++ b/arch/x86/lib/x86-opcode-map.txt @@ -1037,9 +1037,9 @@ EndTable GrpTable: Grp15 0: fxsave | RDFSBASE Ry (F3),(11B) -1: fxstor | RDGSBASE Ry (F3),(11B) -2: vldmxcsr Md (v1) | WRFSBASE Ry (F3),(11B) -3: vstmxcsr Md (v1) | WRGSBASE Ry (F3),(11B) +1: fxrstor | RDGSBASE Ry (F3),(11B) +2: ldmxcsr | vldmxcsr Md (v1) | WRFSBASE Ry (F3),(11B) +3: stmxcsr | vstmxcsr Md (v1) | WRGSBASE Ry (F3),(11B) 4: XSAVE | ptwrite Ey (F3),(11B) 5: XRSTOR | lfence (11B) | INCSSPD/Q Ry (F3),(11B) 6: XSAVEOPT | clwb (66) | mfence (11B) | TPAUSE Rd (66),(11B) | UMONITOR Rv (F3),(11B) | UMWAIT Rd (F2),(11B) | CLRSSBSY Mq (F3) diff --git a/arch/x86/tools/gen-insn-attr-x86.awk b/arch/x86/tools/gen-insn-attr-x86.awk index a42015b305f4..21de6757893f 100644 --- a/arch/x86/tools/gen-insn-attr-x86.awk +++ b/arch/x86/tools/gen-insn-attr-x86.awk @@ -65,7 +65,11 @@ BEGIN { modrm_expr = "^([CDEGMNPQRSUVW/][a-z]+|NTA|T[012])" force64_expr = "\\([df]64\\)" rex_expr = "^REX(\\.[XRWB]+)*" - fpu_expr = "^ESC" # TODO + + mmxreg_expr = "^[HLNPQUVW][a-z]+" # MMX/SSE register operands + mmx_expr = "^\\((emms|fxsave|fxrstor|ldmxcsr|stmxcsr)\\)" # MMX/SSE nmemonics lacking operands + mmxifvex_expr = "^(CMOV|SET.*)" # nmemonics NOT an AVX + fpu_expr = "^ESC" lprefix1_expr = "\\((66|!F3)\\)" lprefix2_expr = "\\(F3\\)" @@ -236,10 +240,11 @@ function add_flags(old,new) { } # convert operands to flags. -function convert_operands(count,opnd, i,j,imm,mod) +function convert_operands(count,opnd, i,j,imm,mod,mmx) { imm = null mod = null + mmx = null for (j = 1; j <= count; j++) { i = opnd[j] if (match(i, imm_expr) == 1) { @@ -253,7 +258,12 @@ function convert_operands(count,opnd, i,j,imm,mod) imm = imm_flag[i] } else if (match(i, modrm_expr)) mod = "INAT_MODRM" + if (match(i, mmxreg_expr) == 1) { + mmx = "INAT_FPU" + } } + if (mmx) + imm = add_flags(imm, mmx) return add_flags(imm, mod) } @@ -318,9 +328,11 @@ function convert_operands(count,opnd, i,j,imm,mod) if (match(opcode, rex_expr)) flags = add_flags(flags, "INAT_MAKE_PREFIX(INAT_PFX_REX)") - # check coprocessor escape : TODO - if (match(opcode, fpu_expr)) - flags = add_flags(flags, "INAT_MODRM") + # check coprocessor escape + if (match(opcode, fpu_expr) || match(opcode, mmx_expr)) + flags = add_flags(flags, "INAT_MODRM | INAT_FPU") + if (match(opcode, mmxifvex_expr)) + flags = add_flags(flags, "INAT_FPUIFVEX") # check VEX codes if (match(ext, evexonly_expr)) diff --git a/tools/arch/x86/include/asm/inat.h b/tools/arch/x86/include/asm/inat.h index 877827b7c2c3..2e6a05290efd 100644 --- a/tools/arch/x86/include/asm/inat.h +++ b/tools/arch/x86/include/asm/inat.h @@ -77,6 +77,8 @@ #define INAT_VEXOK (1 << (INAT_FLAG_OFFS + 5)) #define INAT_VEXONLY (1 << (INAT_FLAG_OFFS + 6)) #define INAT_EVEXONLY (1 << (INAT_FLAG_OFFS + 7)) +#define INAT_FPU (1 << (INAT_FLAG_OFFS + 8)) +#define INAT_FPUIFVEX (1 << (INAT_FLAG_OFFS + 9)) /* Attribute making macros for attribute tables */ #define INAT_MAKE_PREFIX(pfx) (pfx << INAT_PFX_OFFS) #define INAT_MAKE_ESCAPE(esc) (esc << INAT_ESC_OFFS) @@ -227,4 +229,9 @@ static inline int inat_must_evex(insn_attr_t attr) { return attr & INAT_EVEXONLY; } + +static inline int inat_is_fpu(insn_attr_t attr) +{ + return attr & INAT_FPU; +} #endif diff --git a/tools/arch/x86/include/asm/insn.h b/tools/arch/x86/include/asm/insn.h index 568854b14d0a..d9f6bd9059c1 100644 --- a/tools/arch/x86/include/asm/insn.h +++ b/tools/arch/x86/include/asm/insn.h @@ -129,6 +129,18 @@ static inline int insn_is_evex(struct insn *insn) return (insn->vex_prefix.nbytes == 4); } +static inline int insn_is_fpu(struct insn *insn) +{ + if (!insn->opcode.got) + insn_get_opcode(insn); + if (inat_is_fpu(insn->attr)) { + if (insn->attr & INAT_FPUIFVEX) + return insn_is_avx(insn); + return 1; + } + return 0; +} + static inline int insn_has_emulate_prefix(struct insn *insn) { return !!insn->emulate_prefix_size; diff --git a/tools/arch/x86/lib/x86-opcode-map.txt b/tools/arch/x86/lib/x86-opcode-map.txt index ec31f5b60323..c3d36b4c894d 100644 --- a/tools/arch/x86/lib/x86-opcode-map.txt +++ b/tools/arch/x86/lib/x86-opcode-map.txt @@ -1037,9 +1037,9 @@ EndTable GrpTable: Grp15 0: fxsave | RDFSBASE Ry (F3),(11B) -1: fxstor | RDGSBASE Ry (F3),(11B) -2: vldmxcsr Md (v1) | WRFSBASE Ry (F3),(11B) -3: vstmxcsr Md (v1) | WRGSBASE Ry (F3),(11B) +1: fxrstor | RDGSBASE Ry (F3),(11B) +2: ldmxcsr | vldmxcsr Md (v1) | WRFSBASE Ry (F3),(11B) +3: stmxcsr | vstmxcsr Md (v1) | WRGSBASE Ry (F3),(11B) 4: XSAVE | ptwrite Ey (F3),(11B) 5: XRSTOR | lfence (11B) | INCSSPD/Q Ry (F3),(11B) 6: XSAVEOPT | clwb (66) | mfence (11B) | TPAUSE Rd (66),(11B) | UMONITOR Rv (F3),(11B) | UMWAIT Rd (F2),(11B) | CLRSSBSY Mq (F3) diff --git a/tools/arch/x86/tools/gen-insn-attr-x86.awk b/tools/arch/x86/tools/gen-insn-attr-x86.awk index a42015b305f4..21de6757893f 100644 --- a/tools/arch/x86/tools/gen-insn-attr-x86.awk +++ b/tools/arch/x86/tools/gen-insn-attr-x86.awk @@ -65,7 +65,11 @@ BEGIN { modrm_expr = "^([CDEGMNPQRSUVW/][a-z]+|NTA|T[012])" force64_expr = "\\([df]64\\)" rex_expr = "^REX(\\.[XRWB]+)*" - fpu_expr = "^ESC" # TODO + + mmxreg_expr = "^[HLNPQUVW][a-z]+" # MMX/SSE register operands + mmx_expr = "^\\((emms|fxsave|fxrstor|ldmxcsr|stmxcsr)\\)" # MMX/SSE nmemonics lacking operands + mmxifvex_expr = "^(CMOV|SET.*)" # nmemonics NOT an AVX + fpu_expr = "^ESC" lprefix1_expr = "\\((66|!F3)\\)" lprefix2_expr = "\\(F3\\)" @@ -236,10 +240,11 @@ function add_flags(old,new) { } # convert operands to flags. -function convert_operands(count,opnd, i,j,imm,mod) +function convert_operands(count,opnd, i,j,imm,mod,mmx) { imm = null mod = null + mmx = null for (j = 1; j <= count; j++) { i = opnd[j] if (match(i, imm_expr) == 1) { @@ -253,7 +258,12 @@ function convert_operands(count,opnd, i,j,imm,mod) imm = imm_flag[i] } else if (match(i, modrm_expr)) mod = "INAT_MODRM" + if (match(i, mmxreg_expr) == 1) { + mmx = "INAT_FPU" + } } + if (mmx) + imm = add_flags(imm, mmx) return add_flags(imm, mod) } @@ -318,9 +328,11 @@ function convert_operands(count,opnd, i,j,imm,mod) if (match(opcode, rex_expr)) flags = add_flags(flags, "INAT_MAKE_PREFIX(INAT_PFX_REX)") - # check coprocessor escape : TODO - if (match(opcode, fpu_expr)) - flags = add_flags(flags, "INAT_MODRM") + # check coprocessor escape + if (match(opcode, fpu_expr) || match(opcode, mmx_expr)) + flags = add_flags(flags, "INAT_MODRM | INAT_FPU") + if (match(opcode, mmxifvex_expr)) + flags = add_flags(flags, "INAT_FPUIFVEX") # check VEX codes if (match(ext, evexonly_expr)) -- 2.20.1 Thank you, -- Masami Hiramatsu <mhiramat@xxxxxxxxxx> _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx