Am 2020-04-01 um 5:00 p.m. schrieb Alex Sierra:
> This reverts commit 9e517bb84c282c1f06edded20f16f927426d2e40.
> Navi ASICs don't require to access through PSP to osssys registers.
> This on SR-IOV configuration.
If you submit this change, please don't forget to add a Signed-off-by
line and feel free to add my Reviewed-by.
But I think we don't need to revert it. Just change the condition for
using PSP. See inline ...
> ---
> drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 89 +++-----------------------
> 1 file changed, 9 insertions(+), 80 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> index 6fca5206833d..4968259a22c4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> @@ -49,30 +49,14 @@ static void navi10_ih_enable_interrupts(struct amdgpu_device *adev)
>
> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
> - if (amdgpu_sriov_vf(adev)) {
Just change this condition to if (amdgpu_sriov_vf(adev) &&
adev->asic_type < CHIP_NAVI10) everywhere.
Regards,
Felix
> - if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) {
> - DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
> - return;
> - }
> - } else {
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
> - }
> -
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
> adev->irq.ih.enabled = true;
>
> if (adev->irq.ih1.ring_size) {
> ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
> RB_ENABLE, 1);
> - if (amdgpu_sriov_vf(adev)) {
> - if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,
> - ih_rb_cntl)) {
> - DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");
> - return;
> - }
> - } else {
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
> - }
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
> adev->irq.ih1.enabled = true;
> }
>
> @@ -80,15 +64,7 @@ static void navi10_ih_enable_interrupts(struct amdgpu_device *adev)
> ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
> RB_ENABLE, 1);
> - if (amdgpu_sriov_vf(adev)) {
> - if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,
> - ih_rb_cntl)) {
> - DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n");
> - return;
> - }
> - } else {
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
> - }
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
> adev->irq.ih2.enabled = true;
> }
> }
> @@ -106,15 +82,7 @@ static void navi10_ih_disable_interrupts(struct amdgpu_device *adev)
>
> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
> - if (amdgpu_sriov_vf(adev)) {
> - if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) {
> - DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
> - return;
> - }
> - } else {
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
> - }
> -
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
> /* set rptr, wptr to 0 */
> WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);
> WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
> @@ -125,15 +93,7 @@ static void navi10_ih_disable_interrupts(struct amdgpu_device *adev)
> ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
> RB_ENABLE, 0);
> - if (amdgpu_sriov_vf(adev)) {
> - if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,
> - ih_rb_cntl)) {
> - DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");
> - return;
> - }
> - } else {
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
> - }
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
> /* set rptr, wptr to 0 */
> WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0);
> WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0);
> @@ -145,15 +105,7 @@ static void navi10_ih_disable_interrupts(struct amdgpu_device *adev)
> ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
> RB_ENABLE, 0);
> - if (amdgpu_sriov_vf(adev)) {
> - if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,
> - ih_rb_cntl)) {
> - DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n");
> - return;
> - }
> - } else {
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
> - }
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
> /* set rptr, wptr to 0 */
> WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0);
> WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0);
> @@ -253,14 +205,7 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev)
> ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl);
> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM,
> !!adev->irq.msi_enabled);
> - if (amdgpu_sriov_vf(adev)) {
> - if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) {
> - DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
> - return -ETIMEDOUT;
> - }
> - } else {
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
> - }
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
> navi10_ih_reroute_ih(adev);
>
> if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) {
> @@ -300,15 +245,7 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev)
> WPTR_OVERFLOW_ENABLE, 0);
> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
> RB_FULL_DRAIN_ENABLE, 1);
> - if (amdgpu_sriov_vf(adev)) {
> - if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,
> - ih_rb_cntl)) {
> - DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");
> - return -ETIMEDOUT;
> - }
> - } else {
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
> - }
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
> /* set rptr, wptr to 0 */
> WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0);
> WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0);
> @@ -326,15 +263,7 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev)
> ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
> ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl);
>
> - if (amdgpu_sriov_vf(adev)) {
> - if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,
> - ih_rb_cntl)) {
> - DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n");
> - return -ETIMEDOUT;
> - }
> - } else {
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
> - }
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
> /* set rptr, wptr to 0 */
> WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0);
> WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0);
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