RE: [PATCH 8/8] drm/amdgpu/smu11: add support for SMU AC/DC interrupts

["Quan, Evan" <Evan.Quan@xxxxxxx>]

I have no target to verify that. The only nv10 board on my hand has no dc/ac automatic switch support.
But it should be correct as windows uses the same client and source id per my confirmation.

Regards,
Evan
-----Original Message-----
From: Alex Deucher <alexdeucher@xxxxxxxxx> 
Sent: Monday, March 23, 2020 10:47 PM
To: Quan, Evan <Evan.Quan@xxxxxxx>
Cc: amd-gfx@xxxxxxxxxxxxxxxxxxxxx; Deucher, Alexander <Alexander.Deucher@xxxxxxx>; mcoffin13@xxxxxxxxx
Subject: Re: [PATCH 8/8] drm/amdgpu/smu11: add support for SMU AC/DC interrupts

On Sun, Mar 22, 2020 at 11:54 PM Quan, Evan <Evan.Quan@xxxxxxx> wrote:
>
> Thanks Alex. The series is reviewed-by: Evan Quan <evan.quan@xxxxxxx>

Thanks Evan.  Can you verify that the client and source id are correct for the interrupt?  I wasn't able to find them.

Alex

>
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of 
> Alex Deucher
> Sent: Saturday, March 21, 2020 2:27 AM
> To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx>; 
> mcoffin13@xxxxxxxxx
> Subject: [PATCH 8/8] drm/amdgpu/smu11: add support for SMU AC/DC 
> interrupts
>
> Driver needs to send the ack message when it receives the AC/DC interrupt from the SMU.
>
> TODO: verify the client and src ids.
>
> Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
> ---
>  drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c 
> b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> index 20174bed11ce..d19e1d0d56c0 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> @@ -1525,6 +1525,13 @@ int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
>         return ret;
>  }
>
> +static int smu_v11_0_ack_ac_dc_interrupt(struct smu_context *smu) {
> +       return smu_send_smc_msg(smu,
> +                               SMU_MSG_ReenableAcDcInterrupt,
> +                               NULL); }
> +
>  #define THM_11_0__SRCID__THM_DIG_THERM_L2H             0               /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH  */
>  #define THM_11_0__SRCID__THM_DIG_THERM_H2L             1               /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL  */
>
> @@ -1558,6 +1565,9 @@ static int smu_v11_0_irq_process(struct amdgpu_device *adev,
>                 break;
>
>                 }
> +       } else if (client_id == SOC15_IH_CLIENTID_MP1) {
> +               if (src_id == 0xfe)
> +                       smu_v11_0_ack_ac_dc_interrupt(&adev->smu);
>         }
>
>         return 0;
> @@ -1597,6 +1607,12 @@ int smu_v11_0_register_irq_handler(struct smu_context *smu)
>         if (ret)
>                 return ret;
>
> +       ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
> +                               0xfe,
> +                               irq_src);
> +       if (ret)
> +               return ret;
> +
>         return ret;
>  }
>
> --
> 2.25.1
>
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