Re: [PATCH] drm/amdgpu: infinite retries fix from UTLC1 RB SDMA

philip yang <yangp@xxxxxxx> · Fri, 20 Mar 2020 21:47:50 -0400

Maybe copy paste typo inline.

Philip

On 2020-03-20 10:41 a.m., Felix Kuehling wrote:
On 2020-03-19 20:27, Alex Sierra wrote:
[Why]
Previously these registers were set to 0. This was causing an
infinite retry on the UTCL1 RB, preventing higher priority RB such as 
paging RB.

[How]
Set to one the SDMAx_UTLC1_TIMEOUT registers for all SDMAs on Arcturus.

Please update this description because the patch is no longer limited 
to Arcturus.

One more comment inline. With those fixed, the patch is

Reviewed-by: Felix Kuehling <Felix.Kuehling@xxxxxxx>



Signed-off-by: Alex Sierra <alex.sierra@xxxxxxx>
---
  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 21 +++++++++++++++++----
  1 file changed, 17 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index fc664ec6b5fd..09c08906046f 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -115,17 +115,21 @@ static const struct soc15_reg_golden 
golden_settings_sdma_4[] = {
  static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
      SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 
0x0018773f, 0x00104002),
      SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104002),
+    SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA0_UTCL1_TIMEOUT, 
0xffffffff, 0x00010001),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 
0x00010001),
      SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 
0xfe931f07, 0x02831d07),
      SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 
0x0018773f, 0x00104002),
-    SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104002)
+    SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104002),
+    SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 
0xffffffff, 0x00010001),
  };
    static const struct soc15_reg_golden golden_settings_sdma_vg12[] = {
      SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 
0x0018773f, 0x00104001),
      SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104001),
+    SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA1_UTCL1_TIMEOUT, 
0xffffffff, 0x00010001),

mmSDMA0_UTCL1_TIMEOUT, although this is same register offset value, it's 
better to use register offset name same as IP block name

      SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 
0xfe931f07, 0x02831d07),
      SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 
0x0018773f, 0x00104001),
-    SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104001)
+    SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104001),
+    SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 
0xffffffff, 0x00010001),
  };
    static const struct soc15_reg_golden golden_settings_sdma_4_1[] = {
@@ -174,6 +178,7 @@ static const struct soc15_reg_golden 
golden_settings_sdma0_4_2[] =
      SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 
0xfffffffd, 0x00000001),
      SOC15_REG_GOLDEN_VALUE(SDMA0, 0, 
mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
      SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 
0x000003ff, 0x000003c0),
+    SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA1_UTCL1_TIMEOUT, 
0xffffffff, 0x00010001),
mmSDMA0_UTCL1_TIMEOUT
  };
    static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = {
@@ -203,6 +208,7 @@ static const struct soc15_reg_golden 
golden_settings_sdma1_4_2[] = {
      SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 
0xfffffffd, 0x00000001),
      SOC15_REG_GOLDEN_VALUE(SDMA1, 0, 
mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
      SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 
0x000003ff, 0x000003c0),
+    SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 
0xffffffff, 0x00010001),
  };
    static const struct soc15_reg_golden golden_settings_sdma_rv1[] =
@@ -222,27 +228,35 @@ static const struct soc15_reg_golden 
golden_settings_sdma_arct[] =
      SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 
0xfe931f07, 0x02831f07),
      SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 
0x0000773f, 0x00004002),
      SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 
0x0000773f, 0x00004002),
+    SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 
0xffffffff, 0x00010001),
      SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 
0xfe931f07, 0x02831f07),
      SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 
0x0000773f, 0x00004002),
      SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 
0x0000773f, 0x00004002),
+    SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 
0xffffffff, 0x00010001),
      SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 
0xfe931f07, 0x02831f07),
      SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 
0x0000773f, 0x00004002),
      SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 
0x0000773f, 0x00004002),
+    SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_UTCL1_TIMEOUT, 
0xffffffff, 0x00010001),
      SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 
0xfe931f07, 0x02831f07),
      SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 
0x0000773f, 0x00004002),
      SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 
0x0000773f, 0x00004002),
+    SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 
0xffffffff, 0x00010001),
      SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_CHICKEN_BITS, 
0xfe931f07, 0x02831f07),
      SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 
0x0000773f, 0x00004002),
      SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 
0x0000773f, 0x00004002),
+    SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 
0xffffffff, 0x00010001),
      SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_CHICKEN_BITS, 
0xfe931f07, 0x02831f07),
      SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG, 
0x0000773f, 0x00004002),
      SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG_READ, 
0x0000773f, 0x00004002),
+    SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_UTCL1_TIMEOUT, 
0xffffffff, 0x00010001),
      SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_CHICKEN_BITS, 
0xfe931f07, 0x02831f07),
      SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG, 
0x0000773f, 0x00004002),
      SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG_READ, 
0x0000773f, 0x00004002),
+    SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_UTCL1_TIMEOUT, 
0xffffffff, 0x00010001),
      SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_CHICKEN_BITS, 
0xfe931f07, 0x02831f07),
      SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG, 
0x0000773f, 0x00004002),
-    SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 
0x0000773f, 0x00004002)
+    SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 
0x0000773f, 0x00004002),
+    SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_UTCL1_TIMEOUT, 
0xffffffff, 0x00010001)
  };
    static const struct soc15_reg_golden golden_settings_sdma_4_3[] = {
@@ -2011,7 +2025,6 @@ static int sdma_v4_0_process_trap_irq(struct 
amdgpu_device *adev,
                        struct amdgpu_iv_entry *entry)
  {
      uint32_t instance;
-

This is an unrelated whitespace change. And I think this would cause 
checkpatch.pl to complain (missing blank line after declarations).


      DRM_DEBUG("IH: SDMA trap\n");
      instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
      switch (entry->ring_id) {
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