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[AMD Public Use]
This seems kind of complicated and error prone. I didn't realize the extent to the changes required. I think it would be better to either add arcturus specific versions of these functions or just go with your original approach and add a new arcturus_ih.c.
If you go with the second route however, no need to show all your intermediate steps, just add the new files in one commit.
Alex
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> on behalf of Alex Sierra <alex.sierra@xxxxxxx>
Sent: Thursday, March 19, 2020 8:22 PM To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx <amd-gfx@xxxxxxxxxxxxxxxxxxxxx> Cc: Sierra Guiza, Alejandro (Alex) <Alex.Sierra@xxxxxxx> Subject: [PATCH 1/4] drm/amdgpu: add stride to calculate oss ring offsets Arcturus and vega10 share the same vega10_ih, however both
have different register offsets at the ih ring section. This variable is used to help calculate ih ring register addresses from the osssys, that corresponds to the current asic type. Signed-off-by: Alex Sierra <alex.sierra@xxxxxxx> --- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h | 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index 5ed4227f304b..fa384ae9a9bc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -279,6 +279,10 @@ int amdgpu_irq_init(struct amdgpu_device *adev) amdgpu_hotplug_work_func); } + if (adev->asic_type == CHIP_ARCTURUS) + adev->irq.ring_stride = 1; + else + adev->irq.ring_stride = 0; INIT_WORK(&adev->irq.ih1_work, amdgpu_irq_handle_ih1); INIT_WORK(&adev->irq.ih2_work, amdgpu_irq_handle_ih2); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h index c718e94a55c9..1ec5b735cd9e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h @@ -97,6 +97,7 @@ struct amdgpu_irq { struct irq_domain *domain; /* GPU irq controller domain */ unsigned virq[AMDGPU_MAX_IRQ_SRC_ID]; uint32_t srbm_soft_reset; + unsigned ring_stride; }; void amdgpu_irq_disable_all(struct amdgpu_device *adev); -- 2.17.1 _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://nam11.safelinks.protection.outlook.com/?url=""> |
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