This macro calculates the IH ring register offset based on the three ring numbers and asic type. The parameters needed are the register's name without the prefix mmIH and the ring number taken from RING0, RING1 or RING2 macros. Signed-off-by: Alex Sierra <alex.sierra@xxxxxxx> --- drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c index 407c6093c2ec..5bd9bc37fadf 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c @@ -34,6 +34,11 @@ #include "vega10_ih.h" #define MAX_REARM_RETRY 10 +#define RING0 0 +#define RING1 (RING0 + 4) +#define RING2 (RING1 + 4) + +#define mmIH_RING_REG(reg, ring) (SOC15_REG_OFFSET(OSSSYS, 0, mmIH_##reg) + (ring) * adev->irq.ring_stride) static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev); -- 2.17.1 _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx
