We hit gmc page fault on navi1X. UMR tells that the physical address of pte is bad. Two issues: 1) we did not sync job schedule fence while update mapping. fix it by adding bo fence to resv after every job submit. 2) we might unref page table bo during update ptes, at the same time, there is job pending on bo. and submit a job in commit after free bo. We need free the bo after adding all fence to bo. change from v2: use the correct page table bo resv change from v1: fix rebase issue. xinhui pan (2): drm/amdgpu: Add job fence to resv conditionally drm/amdgpu: unref the bo after job submit drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 42 +++++++++++++++------ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 5 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 7 ++++ 3 files changed, 42 insertions(+), 12 deletions(-) -- 2.17.1 _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx
