[AMD Official Use Only - Internal Distribution Only]
We can also define a macro to replace the code, and only the macro should be updated for new ASICs in the future.
But either way is fine for me currently, the patch is:
Reviewed-by: Tao Zhou <tao.zhou1@xxxxxxx>
> -----Original Message-----
> From: Chen, Guchun <Guchun.Chen@xxxxxxx>
> Sent: 2020年3月4日 22:47
> To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx; Zhang, Hawking
> <Hawking.Zhang@xxxxxxx>; Li, Dennis <Dennis.Li@xxxxxxx>; Zhou1, Tao
> <Tao.Zhou1@xxxxxxx>; Clements, John <John.Clements@xxxxxxx>
> Cc: Chen, Guchun <Guchun.Chen@xxxxxxx>
> Subject: [PATCH] drm/amdgpu: toggle DF-Cstate when accessing UMC ras
> error related registers
>
> On arcturus, DF-Cstate needs to be toggled off/on before and after accessing
> UMC error counter and error address registers, otherwise, clearing such
> registers may fail.
>
> Signed-off-by: Guchun Chen <guchun.chen@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/umc_v6_1.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
> b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
> index e6866f038209..77122a7282e7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
> @@ -186,6 +186,10 @@ static void umc_v6_1_query_ras_error_count(struct
> amdgpu_device *adev,
> if (rsmu_umc_index_state)
> umc_v6_1_disable_umc_index_mode(adev);
>
> + if ((adev->asic_type == CHIP_ARCTURUS) &&
> + amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
> + DRM_WARN("Fail to disable DF-Cstate.\n");
> +
> LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
> umc_reg_offset = get_umc_6_reg_offset(adev,
> umc_inst,
> @@ -199,6 +203,10 @@ static void umc_v6_1_query_ras_error_count(struct
> amdgpu_device *adev,
> &(err_data-
> >ue_count));
> }
>
> + if ((adev->asic_type == CHIP_ARCTURUS) &&
> + amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW))
> + DRM_WARN("Fail to enable DF-Cstate\n");
> +
> if (rsmu_umc_index_state)
> umc_v6_1_enable_umc_index_mode(adev);
> }
> @@ -288,6 +296,10 @@ static void
> umc_v6_1_query_ras_error_address(struct amdgpu_device *adev,
> if (rsmu_umc_index_state)
> umc_v6_1_disable_umc_index_mode(adev);
>
> + if ((adev->asic_type == CHIP_ARCTURUS) &&
> + amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
> + DRM_WARN("Fail to disable DF-Cstate.\n");
> +
> LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
> umc_reg_offset = get_umc_6_reg_offset(adev,
> umc_inst,
> @@ -300,6 +312,10 @@ static void
> umc_v6_1_query_ras_error_address(struct amdgpu_device *adev,
> umc_inst);
> }
>
> + if ((adev->asic_type == CHIP_ARCTURUS) &&
> + amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW))
> + DRM_WARN("Fail to enable DF-Cstate\n");
> +
> if (rsmu_umc_index_state)
> umc_v6_1_enable_umc_index_mode(adev);
> }
> --
> 2.17.1
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