On 2/27/20 5:44 AM, Alex Deucher wrote:
On Wed, Feb 26, 2020 at 3:34 PM Nirmoy Das <nirmoy.aiemd@xxxxxxxxx> wrote:init_priority will set second compute queue(gfx8 and gfx9) of a pipe to high priority and 1st queue to normal priority. Signed-off-by: Nirmoy Das <nirmoy.das@xxxxxxx> --- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 + drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 14 ++++++++++++++ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 13 +++++++++++++ 3 files changed, 28 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index 24caff085d00..a109373b9fe8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -170,6 +170,7 @@ struct amdgpu_ring_funcs { /* priority functions */ void (*set_priority) (struct amdgpu_ring *ring, enum drm_sched_priority priority); + void (*init_priority) (struct amdgpu_ring *ring); /* Try to soft recover the ring to make the fence signal */ void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid); int (*preempt_ib)(struct amdgpu_ring *ring); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index fa245973de12..14bab6e08bd6 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -6334,6 +6334,19 @@ static void gfx_v8_0_ring_set_priority_compute(struct amdgpu_ring *ring, gfx_v8_0_pipe_reserve_resources(adev, ring, acquire); } +static void gfx_v8_0_ring_init_priority_compute(struct amdgpu_ring *ring) +{ + /* set pipe 0 to normal priority and pipe 1 to high priority*/ + if (ring->queue == 1) { + gfx_v8_0_hqd_set_priority(ring->adev, ring, true); + gfx_v8_0_ring_set_pipe_percent(ring, true); + } else { + gfx_v8_0_hqd_set_priority(ring->adev, ring, false); + gfx_v8_0_ring_set_pipe_percent(ring, false); + } + +}We should drop gfx_v8_0_hqd_set_priority() and set the priorities in the mqd instead. In gfx_v8_0_mqd_init(), set mqd->cp_hqd_pipe_priority and mqd->cp_hqd_queue_priority as appropriate for each queue. I'm not sure we want to mess with gfx_v8_0_ring_set_pipe_percent ultimately at all once this lands. That stuff statically adjusts the priorities between gfx and compute.
Thanks Alex. I will send a updated patch for this.
+ static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring, u64 addr, u64 seq, unsigned flags) @@ -6967,6 +6980,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = { .insert_nop = amdgpu_ring_insert_nop, .pad_ib = amdgpu_ring_generic_pad_ib, .set_priority = gfx_v8_0_ring_set_priority_compute, + .init_priority = gfx_v8_0_ring_init_priority_compute, .emit_wreg = gfx_v8_0_ring_emit_wreg, }; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 1c7a16b91686..0c66743fb6f5 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -5143,6 +5143,18 @@ static void gfx_v9_0_ring_set_priority_compute(struct amdgpu_ring *ring, gfx_v9_0_pipe_reserve_resources(adev, ring, acquire); } +static void gfx_v9_0_ring_init_priority_compute(struct amdgpu_ring *ring) +{ + /* set pipe 0 to normal priority and pipe 1 to high priority*/ + if (ring->queue == 1) { + gfx_v9_0_hqd_set_priority(ring->adev, ring, true); + gfx_v9_0_ring_set_pipe_percent(ring, true); + } else { + gfx_v9_0_hqd_set_priority(ring->adev, ring, false); + gfx_v9_0_ring_set_pipe_percent(ring, true); + } +}Same comment as above. Alex+ static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; @@ -6514,6 +6526,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { .insert_nop = amdgpu_ring_insert_nop, .pad_ib = amdgpu_ring_generic_pad_ib, .set_priority = gfx_v9_0_ring_set_priority_compute, + .init_priority = gfx_v9_0_ring_init_priority_compute, .emit_wreg = gfx_v9_0_ring_emit_wreg, .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, -- 2.25.0 _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cnirmoy.das%40amd.com%7Cdfeeaa22459548bb7b9808d7bb3fcb60%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637183754987155471&sdata=CUR%2BxoLBO%2FPSG7B1lyKAgQVcMLr%2BqQRYlHHs3OGFZPA%3D&reserved=0
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