On Tue, Feb 25, 2020 at 9:46 PM Rohit Khaire <Rohit.Khaire@xxxxxxx> wrote:
>
> This change programs CP_ME_CNTL and RLC_CSIB_* through RLC
>
> Signed-off-by: Rohit Khaire <Rohit.Khaire@xxxxxxx>
Acked-by: Alex Deucher <alexander.deucher@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 44f00ecea322..8f99bc6163b7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -1783,11 +1783,11 @@ static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
> adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
>
> /* csib */
> - WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
> + WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
> adev->gfx.rlc.clear_state_gpu_addr >> 32);
> - WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
> + WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
> adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
> - WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
> + WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
>
> return 0;
> }
> @@ -2395,7 +2395,7 @@ static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
> for (i = 0; i < adev->gfx.num_gfx_rings; i++)
> adev->gfx.gfx_ring[i].sched.ready = false;
> }
> - WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
> + WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
>
> for (i = 0; i < adev->usec_timeout; i++) {
> if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
> --
> 2.17.1
>
> _______________________________________________
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> amd-gfx@xxxxxxxxxxxxxxxxxxxxx
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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