On Thu, Feb 6, 2020 at 3:00 PM Samir Dhume <samir.dhume@xxxxxxx> wrote: > > Ported from Vega10. SDMA stress tests sometimes see IRQ lost. > > Signed-off-by: Samir Dhume <samir.dhume@xxxxxxx> Acked-by: Alex Deucher <alexander.deucher@xxxxxxx> > --- > drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 36 ++++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c > index cf557a428298..e08245a446fc 100644 > --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c > +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c > @@ -32,6 +32,7 @@ > #include "soc15_common.h" > #include "navi10_ih.h" > > +#define MAX_REARM_RETRY 10 > > static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev); > > @@ -283,6 +284,38 @@ static void navi10_ih_decode_iv(struct amdgpu_device *adev, > ih->rptr += 32; > } > > +/** > + * navi10_ih_irq_rearm - rearm IRQ if lost > + * > + * @adev: amdgpu_device pointer > + * > + */ > +static void navi10_ih_irq_rearm(struct amdgpu_device *adev, > + struct amdgpu_ih_ring *ih) > +{ > + uint32_t reg_rptr = 0; > + uint32_t v = 0; > + uint32_t i = 0; > + > + if (ih == &adev->irq.ih) > + reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); > + else if (ih == &adev->irq.ih1) > + reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); > + else if (ih == &adev->irq.ih2) > + reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); > + else > + return; > + > + /* Rearm IRQ / re-write doorbell if doorbell write is lost */ > + for (i = 0; i < MAX_REARM_RETRY; i++) { > + v = RREG32_NO_KIQ(reg_rptr); > + if ((v < ih->ring_size) && (v != ih->rptr)) > + WDOORBELL32(ih->doorbell_index, ih->rptr); > + else > + break; > + } > +} > + > /** > * navi10_ih_set_rptr - set the IH ring buffer rptr > * > @@ -297,6 +330,9 @@ static void navi10_ih_set_rptr(struct amdgpu_device *adev, > /* XXX check if swapping is necessary on BE */ > *ih->rptr_cpu = ih->rptr; > WDOORBELL32(ih->doorbell_index, ih->rptr); > + > + if (amdgpu_sriov_vf(adev)) > + navi10_ih_irq_rearm(adev, ih); > } else > WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); > } > -- > 2.20.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx