Re: [PATCH] drm/amd/powerplay: fix navi10 system intermittent reboot issue

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Reviewed-by: Feifei Xu <Feifei.Xu@xxxxxxx>

> On Jan 30, 2020, at 16:59, Evan Quan <Evan.Quan@xxxxxxx> wrote:
> 
> This workaround is needed only for Navi10 12 Gbps SKUs.
> 
> Change-Id: I4bfcb8a8dbff785a159e6a1ed413d93063403ab3
> Signed-off-by: Evan Quan <evan.quan@xxxxxxx>
> ---
> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 18 +++++++
> .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  1 +
> drivers/gpu/drm/amd/powerplay/inc/smu_types.h |  2 +
> .../drm/amd/powerplay/inc/smu_v11_0_ppsmc.h   |  5 +-
> drivers/gpu/drm/amd/powerplay/navi10_ppt.c    | 49 +++++++++++++++++++
> drivers/gpu/drm/amd/powerplay/smu_internal.h  |  3 ++
> 6 files changed, 77 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index fabc46dfb933..9d1075823681 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -21,6 +21,7 @@
>  */
> 
> #include <linux/firmware.h>
> +#include <linux/pci.h>
> 
> #include "pp_debug.h"
> #include "amdgpu.h"
> @@ -1138,6 +1139,23 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
>        ret = smu_system_features_control(smu, true);
>        if (ret)
>            return ret;
> +
> +        if (adev->asic_type == CHIP_NAVI10) {
> +            if ((adev->pdev->device == 0x731f && (adev->pdev->revision == 0xc2 ||
> +                                  adev->pdev->revision == 0xc3 ||
> +                                  adev->pdev->revision == 0xca ||
> +                                  adev->pdev->revision == 0xcb)) ||
> +                (adev->pdev->device == 0x66af && (adev->pdev->revision == 0xf3 ||
> +                                  adev->pdev->revision == 0xf4 ||
> +                                  adev->pdev->revision == 0xf5 ||
> +                                  adev->pdev->revision == 0xf6))) {
> +                ret = smu_disable_umc_cdr_12gbps_workaround(smu);
> +                if (ret) {
> +                    pr_err("Workaround failed to disable UMC CDR feature on 12Gbps SKU!\n");
> +                    return ret;
> +                }
> +            }
> +        }
>    }
>    if (adev->asic_type != CHIP_ARCTURUS) {
>        ret = smu_notify_display_change(smu);
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index b8781820cec1..75c79b52ef03 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -566,6 +566,7 @@ struct pptable_funcs {
>    int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max);
>    int (*override_pcie_parameters)(struct smu_context *smu);
>    uint32_t (*get_pptable_power_limit)(struct smu_context *smu);
> +    int (*disable_umc_cdr_12gbps_workaround)(struct smu_context *smu);
> };
> 
> int smu_load_microcode(struct smu_context *smu);
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
> index d8c9b7f91fcc..a5b4df146713 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
> @@ -170,6 +170,8 @@
>    __SMU_DUMMY_MAP(SetSoftMinJpeg),              \
>    __SMU_DUMMY_MAP(SetHardMinFclkByFreq),        \
>    __SMU_DUMMY_MAP(DFCstateControl), \
> +    __SMU_DUMMY_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE), \
> +    __SMU_DUMMY_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE), \
> 
> #undef __SMU_DUMMY_MAP
> #define __SMU_DUMMY_MAP(type)    SMU_MSG_##type
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_ppsmc.h
> index 373861ddccd0..406bfd187ce8 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_ppsmc.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_ppsmc.h
> @@ -120,7 +120,10 @@
> #define PPSMC_MSG_GetVoltageByDpmOverdrive       0x45
> #define PPSMC_MSG_BacoAudioD3PME                 0x48
> 
> -#define PPSMC_Message_Count                      0x49
> +#define PPSMC_MSG_DALDisableDummyPstateChange    0x49
> +#define PPSMC_MSG_DALEnableDummyPstateChange     0x4A
> +
> +#define PPSMC_Message_Count                      0x4B
> 
> typedef uint32_t PPSMC_Result;
> typedef uint32_t PPSMC_Msg;
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> index a0a342f6127f..3feb339a434e 100644
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> @@ -119,6 +119,8 @@ static struct smu_11_0_cmn2aisc_mapping navi10_message_map[SMU_MSG_MAX_COUNT] =
>    MSG_MAP(PowerDownJpeg,        PPSMC_MSG_PowerDownJpeg),
>    MSG_MAP(BacoAudioD3PME,        PPSMC_MSG_BacoAudioD3PME),
>    MSG_MAP(ArmD3,            PPSMC_MSG_ArmD3),
> +    MSG_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE,PPSMC_MSG_DALDisableDummyPstateChange),
> +    MSG_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE,    PPSMC_MSG_DALEnableDummyPstateChange),
> };
> 
> static struct smu_11_0_cmn2aisc_mapping navi10_clk_map[SMU_CLK_COUNT] = {
> @@ -2127,6 +2129,52 @@ static int navi10_run_btc(struct smu_context *smu)
>    return ret;
> }
> 
> +static int navi10_dummy_pstate_control(struct smu_context *smu, bool enable)
> +{
> +    int result = 0;
> +
> +    if (!enable)
> +        result = smu_send_smc_msg(smu, SMU_MSG_DAL_DISABLE_DUMMY_PSTATE_CHANGE);
> +    else
> +        result = smu_send_smc_msg(smu, SMU_MSG_DAL_ENABLE_DUMMY_PSTATE_CHANGE);
> +
> +    return result;
> +}
> +
> +static int navi10_disable_umc_cdr_12gbps_workaround(struct smu_context *smu)
> +{
> +    uint32_t uclk_count, uclk_min, uclk_max;
> +    int ret = 0;
> +
> +    ret = smu_get_dpm_level_count(smu, SMU_UCLK, &uclk_count);
> +    if (ret)
> +        return ret;
> +
> +    ret = smu_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)0, &uclk_min);
> +    if (ret)
> +        return ret;
> +
> +    ret = smu_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)(uclk_count - 1), &uclk_max);
> +    if (ret)
> +        return ret;
> +
> +    /* Force UCLK out of the highest DPM */
> +    ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, uclk_min);
> +    if (ret)
> +        return ret;
> +
> +    /* Revert the UCLK Hardmax */
> +    ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, uclk_max);
> +    if (ret)
> +        return ret;
> +
> +    /*
> +     * In this case, SMU already disabled dummy pstate during enablement
> +     * of UCLK DPM, we have to re-enabled it.
> +     * */
> +    return navi10_dummy_pstate_control(smu, true);
> +}
> +
> static const struct pptable_funcs navi10_ppt_funcs = {
>    .tables_init = navi10_tables_init,
>    .alloc_dpm_context = navi10_allocate_dpm_context,
> @@ -2221,6 +2269,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
>    .od_edit_dpm_table = navi10_od_edit_dpm_table,
>    .get_pptable_power_limit = navi10_get_pptable_power_limit,
>    .run_btc = navi10_run_btc,
> +    .disable_umc_cdr_12gbps_workaround = navi10_disable_umc_cdr_12gbps_workaround,
> };
> 
> void navi10_set_ppt_funcs(struct smu_context *smu)
> diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h b/drivers/gpu/drm/amd/powerplay/smu_internal.h
> index 783319ec8bf9..7bd200ffcda8 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
> +++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
> @@ -207,4 +207,7 @@ int smu_send_smc_msg(struct smu_context *smu, enum smu_message_type msg);
> #define smu_update_pcie_parameters(smu, pcie_gen_cap, pcie_width_cap) \
>        ((smu)->ppt_funcs->update_pcie_parameters ? (smu)->ppt_funcs->update_pcie_parameters((smu), (pcie_gen_cap), (pcie_width_cap)) : 0)
> 
> +#define smu_disable_umc_cdr_12gbps_workaround(smu) \
> +    ((smu)->ppt_funcs->disable_umc_cdr_12gbps_workaround ? (smu)->ppt_funcs->disable_umc_cdr_12gbps_workaround((smu)) : 0)
> +
> #endif
> -- 
> 2.24.1
> 
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